riscv/rocket-chip
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RegFieldDesc: change how reserved is indicated

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This commit is contained in:
Megan Wachs
2018-03-09 17:38:23 -08:00
parent d889a0ca16
commit 15e058e3da
3 changed files with 10 additions and 10 deletions
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6
src/main/scala/devices/tilelink/Plic.scala
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@ -173,13 +173,13 @@ class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends
reset=if (nPriorities > 0) None else Some(1),
wrType=Some(RegFieldWrType.MODIFY))
} else {
RegFieldDescReserved()
RegFieldDesc.reserved()
}
def pendingRegDesc(i: Int) = if (i > 0) {
RegFieldDesc(s"pending_$i", s"Set to 1 if interrupt source $i is pending, regardless of its enable or priority setting.",
volatile = true)
} else {
RegFieldDescReserved()
RegFieldDesc.reserved()
}
def priorityRegField(x: UInt, i: Int) = if (nPriorities > 0) RegField(32, x, priorityRegDesc(i)) else RegField.r(32, x, priorityRegDesc(i))
@ -195,7 +195,7 @@ class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends
e.zipWithIndex.map{case (b, j) => if (j > 0) {
RegField(1, b, RegFieldDesc(s"enable_${i}_${j}", s"Enable interrupt for source $j for target $i.", reset=None))
} else {
RegField(1, b, RegFieldDescReserved())
RegField(1, b, RegFieldDesc.reserved())
}})
}