riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

tile: removed RocketTileWrapper. RocketTile now HasCrossing.

Browse Source
This commit is contained in:
Henry Cook
2017-12-28 14:00:13 -08:00
parent 1cd018546c
commit 1579ddb97e
5 changed files with 65 additions and 90 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/main/scala/tile/BaseTile.scala
View File

@ -5,7 +5,7 @@ package freechips.rocketchip.tile
import Chisel._
import freechips.rocketchip.config._
import freechips.rocketchip.coreplex.{CacheBlockBytes, SystemBusKey}
import freechips.rocketchip.coreplex._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.interrupts._
import freechips.rocketchip.rocket._
@ -144,8 +144,11 @@ trait CanHaveInstructionTracePort extends Bundle with HasTileParameters {
}
/** Base class for all Tiles that use TileLink */
abstract class BaseTile(tileParams: TileParams)(implicit p: Parameters) extends BareTile
with HasTileParameters {
abstract class BaseTile(
tileParams: TileParams,
val crossing: CoreplexClockCrossing)(implicit p: Parameters) extends BareTile
with HasTileParameters
with HasCrossing {
def module: BaseTileModule[BaseTile, BaseTileBundle[BaseTile]]
def masterNode: TLOutwardNode
def slaveNode: TLInwardNode
@ -156,6 +159,7 @@ abstract class BaseTile(tileParams: TileParams)(implicit p: Parameters) extends
protected val tlMasterXbar = LazyModule(new TLXbar)
protected val tlSlaveXbar = LazyModule(new TLXbar)
protected val intXbar = LazyModule(new IntXbar)
protected val intSinkNode = IntSinkNode(IntSinkPortSimple())
def connectTLSlave(node: TLNode, bytes: Int) {
DisableMonitors { implicit p =>

20
src/main/scala/tile/Interrupts.scala
View File

@ -19,11 +19,10 @@ class TileInterrupts(implicit p: Parameters) extends CoreBundle()(p) {
}
// Use diplomatic interrupts to external interrupts from the coreplex into the tile
trait HasExternalInterrupts extends HasTileParameters {
implicit val p: Parameters
val module: HasExternalInterruptsModule
trait HasExternalInterrupts { this: BaseTile =>
val intInwardNode = IntSinkNode(IntSinkPortSimple())
val intInwardNode = intXbar.intnode
intSinkNode := intXbar.intnode
val intcDevice = new Device {
def describe(resources: ResourceBindings): Description = {
@ -37,7 +36,7 @@ trait HasExternalInterrupts extends HasTileParameters {
ResourceBinding {
Resource(intcDevice, "reg").bind(ResourceInt(BigInt(hartId)))
intInwardNode.edges.in.flatMap(_.source.sources).map { case s =>
intSinkNode.edges.in.flatMap(_.source.sources).map { case s =>
for (i <- s.range.start until s.range.end) {
csrIntMap.lift(i).foreach { j =>
s.resources.foreach { r =>
@ -59,15 +58,6 @@ trait HasExternalInterrupts extends HasTileParameters {
List(65535, 3, 7, 11) ++ seip ++ List.tabulate(nlips)(_ + 16)
}
}
trait HasExternalInterruptsBundle {
val outer: HasExternalInterrupts
}
trait HasExternalInterruptsModule {
val outer: HasExternalInterrupts
// go from flat diplomatic Interrupts to bundled TileInterrupts
def decodeCoreInterrupts(core: TileInterrupts) {
val async_ips = Seq(core.debug)
@ -80,7 +70,7 @@ trait HasExternalInterruptsModule {
val core_ips = core.lip
val (interrupts, _) = outer.intInwardNode.in(0)
val (interrupts, _) = intSinkNode.in(0)
(async_ips ++ periph_ips ++ seip ++ core_ips).zip(interrupts).foreach { case(c, i) => c := i }
}
}

65
src/main/scala/tile/RocketTile.scala
View File

@ -5,11 +5,9 @@ package freechips.rocketchip.tile
import Chisel._
import freechips.rocketchip.config._
import freechips.rocketchip.coreplex._
import freechips.rocketchip.coreplex.CoreplexClockCrossing
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.rocket._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.interrupts._
import freechips.rocketchip.util._
case class RocketTileParams(
@ -30,7 +28,10 @@ case class RocketTileParams(
require(dcache.isDefined)
}
class RocketTile(val rocketParams: RocketTileParams)(implicit p: Parameters) extends BaseTile(rocketParams)(p)
class RocketTile(
val rocketParams: RocketTileParams,
crossing: CoreplexClockCrossing)
(implicit p: Parameters) extends BaseTile(rocketParams, crossing)(p)
with HasExternalInterrupts
with HasLazyRoCC // implies CanHaveSharedFPU with CanHavePTW with HasHellaCache
with CanHaveScratchpad { // implies CanHavePTW with HasHellaCache with HasICacheFrontend
@ -61,14 +62,13 @@ class RocketTileBundle(outer: RocketTile) extends BaseTileBundle(outer)
}
class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => new RocketTileBundle(outer))
with HasExternalInterruptsModule
with HasLazyRoCCModule
with CanHaveScratchpadModule {
val core = Module(p(BuildCore)(outer.p))
val uncorrectable = RegInit(Bool(false))
decodeCoreInterrupts(core.io.interrupts) // Decode the interrupt vector
outer.decodeCoreInterrupts(core.io.interrupts) // Decode the interrupt vector
outer.busErrorUnit.foreach { beu => core.io.interrupts.buserror.get := beu.module.io.interrupt }
core.io.hartid := io.hartid // Pass through the hartid
io.trace.foreach { _ := core.io.trace }
@ -103,56 +103,3 @@ class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => ne
dcacheArb.io.requestor <> dcachePorts
ptw.io.requestor <> ptwPorts
}
class RocketTileWrapperBundle[+L <: RocketTileWrapper](_outer: L) extends BaseTileBundle(_outer)
with CanHaltAndCatchFire {
val halt_and_catch_fire = _outer.rocket.module.io.halt_and_catch_fire.map(_.cloneType)
}
class RocketTileWrapper(
params: RocketTileParams,
val crossing: CoreplexClockCrossing)
(implicit p: Parameters) extends BaseTile(params) with HasCrossing {
val rocket = LazyModule(new RocketTile(params))
// The buffers needed to cut feed-through paths are microarchitecture specific, so belong here
val masterBuffer = LazyModule(new TLBuffer(BufferParams.none, BufferParams.flow, BufferParams.none, BufferParams.flow, BufferParams(1)))
val masterNode = crossing match {
case _: AsynchronousCrossing => rocket.masterNode
case SynchronousCrossing(b) =>
require (!params.boundaryBuffers || (b.depth >= 1 && !b.flow && !b.pipe), "Buffer misconfiguration creates feed-through paths")
rocket.masterNode
case RationalCrossing(dir) =>
require (dir != SlowToFast, "Misconfiguration? Core slower than fabric")
if (params.boundaryBuffers) {
masterBuffer.node :=* rocket.masterNode
} else {
rocket.masterNode
}
}
val slaveBuffer = LazyModule(new TLBuffer(BufferParams.flow, BufferParams.none, BufferParams.none, BufferParams.none, BufferParams.none))
val slaveNode: TLInwardNode = crossing match {
case _: SynchronousCrossing => rocket.slaveNode // requirement already checked
case _: AsynchronousCrossing => rocket.slaveNode
case _: RationalCrossing =>
if (params.boundaryBuffers) {
DisableMonitors { implicit p => rocket.slaveNode :*= slaveBuffer.node }
} else {
rocket.slaveNode
}
}
rocket.intInwardNode := intXbar.intnode
val intInwardNode = intXbar.intnode
val intOutwardNode = rocket.intOutwardNode
override lazy val module = new BaseTileModule(this, () => new RocketTileWrapperBundle(this)) {
// signals that do not change based on crossing type:
rocket.module.io.hartid := io.hartid
rocket.module.io.reset_vector := io.reset_vector
io.trace.foreach { _ := rocket.module.io.trace.get }
io.halt_and_catch_fire.foreach { _ := rocket.module.io.halt_and_catch_fire.get }
}
}