From 1549ecfb3f7e5cd2c920de5ea30d3ecb57943fa3 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Thu, 16 Nov 2017 15:25:41 -0800 Subject: [PATCH] debug: explicitly clone riscv-tests to get to gdbserver.py --- regression/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/regression/Makefile b/regression/Makefile index 48f114df..7a65b8dd 100644 --- a/regression/Makefile +++ b/regression/Makefile @@ -255,7 +255,7 @@ stamps/%/vsim-jtag-dtm-64-$(JTAG_DTM_TEST).stamp: stamps/%/vsim$(JTAG_STAMP_SUFF stamps/%/emulator-jtag-dtm-32-$(JTAG_DTM_TEST).stamp: stamps/%/emulator$(JTAG_STAMP_SUFFIX).stamp stamps/riscv-tests.stamp RISCV=$(RISCV) $(GDBSERVER) \ - --sim_cmd "$(abspath $(TOP))/emulator/emulator-$(PROJECT)-$*$(JTAG_DEBUG_SUFFIX) +verbose $(SEED_ARG) $(EMULATOR_JTAG_VCDPLUS_32) dummybin" \ + --sim_cmd="$(abspath $(TOP))/emulator/emulator-$(PROJECT)-$*$(JTAG_DEBUG_SUFFIX) +verbose $(SEED_ARG) $(EMULATOR_JTAG_VCDPLUS_32) dummybin" \ --server_cmd="$(RISCV)/bin/openocd $(OPENOCD_DEBUG) \ --s $(RISCV)/share/openocd/scripts" \ --32 \ @@ -265,7 +265,7 @@ stamps/%/emulator-jtag-dtm-32-$(JTAG_DTM_TEST).stamp: stamps/%/emulator$(JTAG_S stamps/%/emulator-jtag-dtm-64-$(JTAG_DTM_TEST).stamp: stamps/%/emulator$(JTAG_STAMP_SUFFIX).stamp stamps/riscv-tests.stamp RISCV=$(RISCV) $(GDBSERVER) \ - --sim_cmd "$(abspath $(TOP))/emulator/emulator-$(PROJECT)-$*$(JTAG_DEBUG_SUFFIX) +verbose $(SEED_ARG) $(EMULATOR_JTAG_VCDPLUS_64) dummybin" \ + --sim_cmd="$(abspath $(TOP))/emulator/emulator-$(PROJECT)-$*$(JTAG_DEBUG_SUFFIX) +verbose $(SEED_ARG) $(EMULATOR_JTAG_VCDPLUS_64) dummybin" \ --server_cmd="$(RISCV)/bin/openocd $(OPENOCD_DEBUG) \ --s $(RISCV)/share/openocd/scripts" \ --64 \