Fix AXI4 FIFO ordering for masters with early source reuse (#1108)
* TLToAXI4: fix WaR for single-source FIFO masters * TLToAXI4: fix potential counter overflow => WaR hazard If you have a FIFO master with 2^n-1 sources that performs early source re-use, the old code could potentially break FIFO order.
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@ -191,8 +191,15 @@ class TLToAXI4(val combinational: Boolean = true, val adapterName: Option[String
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val d_sel = UIntToOH(Mux(r_wins, out.r.bits.id, out.b.bits.id), edgeOut.master.endId).toBools
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val d_last = Mux(r_wins, out.r.bits.last, Bool(true))
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// If FIFO was requested, ensure that R+W ordering is preserved
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(a_sel zip d_sel zip idStall zip idCount) filter { case (_, n) => n.map(_ > 1).getOrElse(false) } foreach { case (((as, ds), s), n) =>
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val count = RegInit(UInt(0, width = log2Ceil(n.get + 1)))
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(a_sel zip d_sel zip idStall zip idCount) filter { case (_, n) => n.isDefined } foreach { case (((as, ds), s), n) =>
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// AXI does not guarantee read vs. write ordering. In particular, if we
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// are in the middle of receiving a read burst and then issue a write,
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// the write might affect the read burst. This violates FIFO behaviour.
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// To solve this, we must wait until the last beat of a burst, but this
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// means that there can be idCount+1 operations counted due to a TileLink
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// master which performs early source reuse.
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val maxCount = n.get + 1
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val count = RegInit(UInt(0, width = log2Ceil(maxCount + 1)))
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val write = Reg(Bool())
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val idle = count === UInt(0)
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@ -200,8 +207,8 @@ class TLToAXI4(val combinational: Boolean = true, val adapterName: Option[String
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val dec = ds && d_last && in.d.fire()
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count := count + inc.asUInt - dec.asUInt
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assert (!dec || count =/= UInt(0)) // underflow
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assert (!inc || count =/= UInt(n.get)) // overflow
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assert (!dec || count =/= UInt(0)) // underflow
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assert (!inc || count =/= UInt(maxCount)) // overflow
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when (inc) { write := arw.wen }
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s := !idle && write =/= arw.wen
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