riscv/rocket-chip
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Update TLB interface

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n.b. no need to set mprv, since prv = S.
This commit is contained in:
Andrew Waterman 2016-03-14 17:55:19 -07:00
parent 3e721fe80b
commit 13dcb96b7f
1 changed files with 1 additions and 3 deletions
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4
groundtest/src/main/scala/tile.scala
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@ -58,7 +58,6 @@ class DummyPTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
val s2_valid = Reg(next = req_arb.io.out.valid) val s2_valid = Reg(next = req_arb.io.out.valid)
val s2_resp = Wire(new PTWResp) val s2_resp = Wire(new PTWResp)
s2_resp.error := Bool(false)
s2_resp.pte.ppn := s2_ppn s2_resp.pte.ppn := s2_ppn
s2_resp.pte.reserved_for_software := UInt(0) s2_resp.pte.reserved_for_software := UInt(0)
s2_resp.pte.d := Bool(true) s2_resp.pte.d := Bool(true)
@ -69,9 +68,8 @@ class DummyPTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
io.requestors.zipWithIndex.foreach { case (requestor, i) => io.requestors.zipWithIndex.foreach { case (requestor, i) =>
requestor.resp.valid := s2_valid && s2_chosen === UInt(i) requestor.resp.valid := s2_valid && s2_chosen === UInt(i)
requestor.resp.bits := s2_resp requestor.resp.bits := s2_resp
requestor.status.mprv := Bool(false)
requestor.status.vm := UInt("b01000") requestor.status.vm := UInt("b01000")
requestor.status.prv := UInt(PRV_S) requestor.status.prv := UInt(PRV.S)
} }
} }