riscv/rocket-chip
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diplomacy: implement DisableMonitors scope

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This commit is contained in:
Wesley W. Terpstra
2017-09-07 14:25:33 -07:00
parent a450357744
commit 1365c5f90c
5 changed files with 36 additions and 24 deletions
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18
src/main/scala/tile/RocketTile.scala
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@ -191,7 +191,7 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p:
def optionalSlaveBuffer(in: TLOutwardNode): TLOutwardNode = {
if (rtp.boundaryBuffers) {
val sbuf = LazyModule(new TLBuffer(BufferParams.flow, BufferParams.none, BufferParams.none, BufferParams.none, BufferParams.none))
sbuf.node connectButDontMonitorSlaves in
DisableMonitors { implicit p => sbuf.node :*= in }
sbuf.node
} else {
in
@ -217,7 +217,7 @@ class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters)
masterNode :=* optionalMasterBuffer(rocket.masterNode)
val slaveNode = new TLInputNode() { override def reverse = true }
rocket.slaveNode connectButDontMonitorSlaves optionalSlaveBuffer(slaveNode)
DisableMonitors { implicit p => rocket.slaveNode :*= optionalSlaveBuffer(slaveNode) }
// Fully async interrupts need synchronizers.
// Others need no synchronization.
@ -237,8 +237,11 @@ class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters
val slaveNode = new TLAsyncInputNode() { override def reverse = true }
val sink = LazyModule(new TLAsyncCrossingSink)
rocket.slaveNode connectButDontMonitorSlaves sink.node
sink.node connectButDontMonitorSlaves slaveNode
DisableMonitors { implicit p =>
rocket.slaveNode :*= sink.node
sink.node :*= slaveNode
}
// Fully async interrupts need synchronizers,
// as do those coming from the periphery clock.
@ -261,8 +264,11 @@ class RationalRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Paramet
val slaveNode = new TLRationalInputNode() { override def reverse = true }
val sink = LazyModule(new TLRationalCrossingSink(SlowToFast))
sink.node connectButDontMonitorSlaves slaveNode
rocket.slaveNode connectButDontMonitorSlaves optionalSlaveBuffer(sink.node)
DisableMonitors { implicit p =>
sink.node :*= slaveNode
rocket.slaveNode :*= optionalSlaveBuffer(sink.node)
}
// Fully async interrupts need synchronizers.
// Those coming from periphery clock need a