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Fix the SCR file for Chisel 3

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This commit is contained in:
Palmer Dabbelt 2016-03-05 17:20:54 -08:00
parent c13b8d243d
commit 1344d09cef
1 changed files with 4 additions and 35 deletions
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35
uncore/src/main/scala/scr.scala
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@ -41,50 +41,19 @@ class SCRIO(map: SCRFileMap)(implicit p: Parameters) extends HtifBundle()(p) {
val waddr = UInt(OUTPUT, log2Up(nSCR))
val wdata = Bits(OUTPUT, scrDataBits)
def attach(regs: Seq[Data]): Seq[Data] = {
regs.zipWithIndex.map{ case(reg, i) => attach(reg) }
}
def attach(regs: Seq[Data], name_base: String): Seq[Data] = {
regs.zipWithIndex.map{ case(reg, i) => attach(reg, name_base + "__" + i) }
}
def attach(data: Data): Data = attach(data, data.name, false, false)
def attach(data: Data, name: String): Data = attach(data, name, false, false)
def attach(data: Data, addReg: Boolean): Data = attach(data, data.name, false, false)
def attach(data: Data, addReg: Boolean, readOnly: Boolean): Data = attach(data, data.name, readOnly, false)
def attach(data: Data, name: String, addReg: Boolean): Data = attach(data, name, addReg, false)
def attach(data: Data, name: String, addReg: Boolean, readOnly: Boolean): Data = {
def attach(reg: Data, name: String): Data = {
val addr = map.allocate(name)
val reg = if(addReg) { Reg(init = Bits(0, width=data.getWidth)) } else { data }
if (!readOnly) {
when (wen && (waddr === UInt(addr))) {
reg := wdata(data.getWidth-1,0)
reg := wdata
}
}
require(data.getWidth <= scrDataBits, "SCR Width must be <= %d for %s".format(scrDataBits,name))
if (data.getWidth < scrDataBits) {
rdata(addr) := Cat(UInt(0, width=(scrDataBits-data.getWidth)),reg)
} else {
rdata(addr) := reg
}
reg
}
def attach(bundle: Bundle): Array[Data] = attach(bundle, "")
def attach(bundle: Bundle, prefix: String): Array[Data] = {
bundle.flatten.map { x =>
if (x._2.dir == OUTPUT) {
attach(x._2, prefix + x._1, false, true)
} else {
attach(x._2, prefix + x._1, true)
}
}
}
def allocate(address: Int, name: String): Unit = {
map.allocate(address, name)
}