Fix the SCR file for Chisel 3
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		@@ -41,50 +41,19 @@ class SCRIO(map: SCRFileMap)(implicit p: Parameters) extends HtifBundle()(p) {
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  val waddr = UInt(OUTPUT, log2Up(nSCR))
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  val wdata = Bits(OUTPUT, scrDataBits)
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  def attach(regs: Seq[Data]): Seq[Data] = {
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    regs.zipWithIndex.map{ case(reg, i) => attach(reg) }
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  }
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  def attach(regs: Seq[Data], name_base: String): Seq[Data] = {
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    regs.zipWithIndex.map{ case(reg, i) => attach(reg, name_base + "__" + i) }
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  }
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  def attach(data: Data): Data = attach(data, data.name, false, false)
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  def attach(data: Data, name: String): Data = attach(data, name, false, false)
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  def attach(data: Data, addReg: Boolean): Data = attach(data, data.name, false, false)
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  def attach(data: Data, addReg: Boolean, readOnly: Boolean): Data = attach(data, data.name, readOnly, false)
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  def attach(data: Data, name: String, addReg: Boolean): Data = attach(data, name, addReg, false)
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  def attach(data: Data, name: String, addReg: Boolean, readOnly: Boolean): Data = {
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  def attach(reg: Data, name: String): Data = {
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    val addr = map.allocate(name)
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    val reg = if(addReg) { Reg(init = Bits(0, width=data.getWidth)) } else { data }
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    if (!readOnly) {
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      when (wen && (waddr === UInt(addr))) {
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        reg := wdata(data.getWidth-1,0)
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      }
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    }
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    require(data.getWidth <= scrDataBits, "SCR Width must be <= %d for %s".format(scrDataBits,name))
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    if (data.getWidth < scrDataBits) {
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      rdata(addr) := Cat(UInt(0, width=(scrDataBits-data.getWidth)),reg)
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    } else {
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      rdata(addr) := reg
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    when (wen && (waddr === UInt(addr))) {
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      reg := wdata
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    }
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    rdata(addr) := reg
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    reg
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  }
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  def attach(bundle: Bundle): Array[Data] = attach(bundle, "")
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  def attach(bundle: Bundle, prefix: String): Array[Data] = {
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    bundle.flatten.map { x =>
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      if (x._2.dir == OUTPUT) {
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        attach(x._2, prefix + x._1, false, true)
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      } else {
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        attach(x._2, prefix + x._1, true)
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      }
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    }
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  }
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  def allocate(address: Int, name: String): Unit = {
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    map.allocate(address, name)
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  }
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