parent
4eb261c895
commit
1322a02637
@ -282,7 +282,10 @@ class HastiXbar(nMasters: Int, addressMap: Seq[UInt=>Bool])(implicit p: Paramete
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// However, if no slave is connected, for progress report ready anyway, if:
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// bad address (swallow request) OR idle (permit stupid masters to move FSM)
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val autoready = nowhereM(m) || masters(m).isIdle()
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val hready = Mux1H(unionGrantMS(m), slaves.map(_.hready ^ autoready)) ^ autoready
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val hready = if (nSlaves == 1)
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Mux(unionGrantMS(m)(0), slaves(0).hready ^ autoready, Bool(false)) ^ autoready
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else
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Mux1H(unionGrantMS(m), slaves.map(_.hready ^ autoready)) ^ autoready
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masters(m).hready := hready
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// If we diverted a master, we need to absorb his address phase to replay later
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diversions(m).io.divert := (bubbleM(m) || blockedM(m)) && NSeq(m) && hready
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