diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala
index 5d126f2e..ebd39d8f 100644
--- a/rocket/src/main/scala/dpath_util.scala
+++ b/rocket/src/main/scala/dpath_util.scala
@@ -121,7 +121,7 @@ class rocketDpathPCR extends Component
   
   val rdata = Bits();
 
-  val raddr = Mux(io.r.en, io.r.addr, io.host.pcr_req.bits.addr)
+  val raddr = Mux(io.r.en, io.r.addr, io.host.pcr_req.bits.addr(4,0))
   io.host.pcr_rep.valid := io.host.pcr_req.valid && !io.r.en && !io.host.pcr_req.bits.rw
   io.host.pcr_rep.bits := rdata
 
@@ -200,7 +200,6 @@ class rocketDpathPCR extends Component
     when (waddr === PCR_COREID)   { reg_coreid := wdata(15,0) }
     when (waddr === PCR_FROMHOST) { reg_fromhost := wdata; reg_tohost := Bits(0) }
     when (waddr === PCR_TOHOST)   { reg_tohost := wdata; reg_fromhost := Bits(0) }
-    when (waddr === PCR_SEND_IPI) { io.host.ipi.valid := Bool(true) }
     when (waddr === PCR_CLR_IPI)  { r_irq_ipi := wdata(0) }
     when (waddr === PCR_K0)       { reg_k0 := wdata; }
     when (waddr === PCR_K1)       { reg_k1 := wdata; }
diff --git a/rocket/src/main/scala/htif.scala b/rocket/src/main/scala/htif.scala
index 3ee4d533..8a9af58b 100644
--- a/rocket/src/main/scala/htif.scala
+++ b/rocket/src/main/scala/htif.scala
@@ -18,7 +18,7 @@ class ioHost(w: Int) extends Bundle
 class PCRReq extends Bundle
 {
   val rw = Bool()
-  val addr = Bits(width = 5)
+  val addr = Bits(width = 6)
   val data = Bits(width = 64)
 }
 
@@ -75,7 +75,7 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C
 
   val cmd_readmem :: cmd_writemem :: cmd_readcr :: cmd_writecr :: cmd_ack :: cmd_nack :: Nil = Enum(6) { UFix() }
 
-  val pcr_addr = addr(4,0)
+  val pcr_addr = addr(io.cpu(0).pcr_req.bits.addr.width-1, 0)
   val pcr_coreid = if (ncores == 1) UFix(0) else addr(20+log2Up(ncores),20)
   val pcr_wdata = packet_ram(0)