From 130b24355f67fcbade119814cad7c408932f8cb3 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Thu, 24 Aug 2017 17:39:07 -0700
Subject: [PATCH] syncregs: Use synchronizer primitives for IntXing

---
 src/main/scala/tilelink/IntNodes.scala | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/main/scala/tilelink/IntNodes.scala b/src/main/scala/tilelink/IntNodes.scala
index aa910f5b..3b9cab83 100644
--- a/src/main/scala/tilelink/IntNodes.scala
+++ b/src/main/scala/tilelink/IntNodes.scala
@@ -6,6 +6,7 @@ import Chisel._
 import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.util.SynchronizerShiftReg
 import scala.collection.mutable.ListBuffer
 import scala.math.max
 
@@ -139,7 +140,7 @@ class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
     }
 
     (io.in zip io.out) foreach { case (in, out) =>
-      out := (0 to sync).foldLeft(in) { case (a, _) => RegNext(a) }
+      out := SynchronizerShiftReg(in, sync)
     }
   }
 }