From 12d0d8bea27e29e290251dc0e8d2a8d3a39f78fd Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Thu, 17 Nov 2016 14:30:15 -0800
Subject: [PATCH] rocketchip: remove obsolete bus configuration

---
 src/main/scala/rocketchip/Configs.scala   | 11 ------
 src/main/scala/rocketchip/Periphery.scala | 41 -----------------------
 2 files changed, 52 deletions(-)

diff --git a/src/main/scala/rocketchip/Configs.scala b/src/main/scala/rocketchip/Configs.scala
index d4c64ffd..94868680 100644
--- a/src/main/scala/rocketchip/Configs.scala
+++ b/src/main/scala/rocketchip/Configs.scala
@@ -39,9 +39,7 @@ class BasePlatformConfig extends Config(
         case PeripheryBusConfig => TLBusConfig(beatBytes = 4)
         case PeripheryBusArithmetic => true
         // Note that PLIC asserts that this is > 0.
-        case AsyncDebugBus => false
         case IncludeJtagDTM => false
-        case AsyncBusChannels => false
         case NExtBusAXIChannels => 0
         case HastiId => "Ext"
         case HastiKey("TL") =>
@@ -52,9 +50,7 @@ class BasePlatformConfig extends Config(
           HastiParameters(
             addrBits = site(PAddrBits),
             dataBits = edgeDataBits)
-        case AsyncMemChannels => false
         case NMemoryChannels => Dump("N_MEM_CHANNELS", 1)
-        case TMemoryChannels => BusType.AXI
         case ExtMemBase => Dump("MEM_BASE", 0x80000000L)
         case ExtMemSize => Dump("MEM_SIZE", 0x10000000L)
         case ExtBusBase => 0x60000000L
@@ -156,13 +152,6 @@ class TinyConfig extends Config(
   new WithSmallCores ++ new WithRV32 ++
   new WithStatelessBridge ++ new BaseConfig)
 
-class WithAsyncDebug extends Config (
-  (pname, site, here) => pname match {
-    case AsyncDebugBus => true
-    case _ => throw new CDEMatchError
-  }
-)
-
 class WithJtagDTM extends Config (
   (pname, site, here) => pname match {
     case IncludeJtagDTM => true
diff --git a/src/main/scala/rocketchip/Periphery.scala b/src/main/scala/rocketchip/Periphery.scala
index 570a6ea0..8016fd53 100644
--- a/src/main/scala/rocketchip/Periphery.scala
+++ b/src/main/scala/rocketchip/Periphery.scala
@@ -19,23 +19,8 @@ import rocket.XLen
 import scala.math.max
 import coreplex._
 
-/** Options for memory bus interface */
-object BusType {
-  sealed trait EnumVal
-  case object AXI extends EnumVal
-  case object AHB extends EnumVal
-  case object TL  extends EnumVal
-  val busTypes = Seq(AXI, AHB, TL)
-}
-
-/** Memory channel controls */
-case object TMemoryChannels extends Field[BusType.EnumVal]
 /** External Bus controls */
 case object NExtBusAXIChannels extends Field[Int]
-/** Async configurations */
-case object AsyncBusChannels extends Field[Boolean]
-case object AsyncDebugBus extends Field[Boolean]
-case object AsyncMemChannels extends Field[Boolean]
 /** Specifies the size of external memory */
 case object ExtMemSize extends Field[Long]
 case object ExtMemBase extends Field[Long]
@@ -55,36 +40,10 @@ case object SOCBusConfig extends Field[TLBusConfig]
 case object EdgeDataBits extends Field[Int]
 case object EdgeIDBits extends Field[Int]
 
-object PeripheryUtils {
-  def addQueueAXI(source: NastiIO) = {
-    val sink = Wire(source)
-    sink.ar  <> Queue(source.ar, 1)
-    sink.aw  <> Queue(source.aw, 1)
-    sink.w   <> Queue(source.w)
-    source.r <> Queue(sink.r)
-    source.b <> Queue(sink.b, 1)
-    sink
-  }
-  def convertTLtoAXI(tl: ClientUncachedTileLinkIO) = {
-    val bridge = Module(new NastiIOTileLinkIOConverter()(tl.p))
-    bridge.io.tl <> tl
-    addQueueAXI(bridge.io.nasti)
-  }
-  def convertTLtoAHB(tl: ClientUncachedTileLinkIO, atomics: Boolean) = {
-    val bridge = Module(new AHBBridge(atomics)(tl.p))
-    bridge.io.tl <> tl
-    bridge.io.ahb
-  }
-}
-
 /** Utility trait for quick access to some relevant parameters */
 trait HasPeripheryParameters {
   implicit val p: Parameters
-  lazy val tMemChannels = p(TMemoryChannels)
   lazy val nMemChannels = p(NMemoryChannels)
-  lazy val nMemAXIChannels = if (tMemChannels == BusType.AXI) nMemChannels else 0
-  lazy val nMemAHBChannels = if (tMemChannels == BusType.AHB) nMemChannels else 0
-  lazy val nMemTLChannels  = if (tMemChannels == BusType.TL)  nMemChannels else 0
   lazy val peripheryBusConfig = p(PeripheryBusConfig)
   lazy val socBusConfig = p(SOCBusConfig)
   lazy val cacheBlockBytes = p(CacheBlockBytes)