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wip: new network classes

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This commit is contained in:
Henry Cook 2012-12-06 18:51:30 -08:00
parent 8103676b37
commit 12caa55dc7
1 changed files with 66 additions and 0 deletions
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66
uncore/src/tilelink.scala
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@ -3,6 +3,72 @@ package uncore
import Chisel._ import Chisel._
import Constants._ import Constants._
case class PhysicalNetworkConfiguration(nEndpoints: Int, idBits: Int)
class PhysicalHeader(implicit conf: PhysicalNetworkConfiguration) extends Bundle {
val src = UFix(width = conf.idBits)
val dst = UFix(width = conf.idBits)
}
class BasicCrossbarIO[T <: Data]()(data: => T)(implicit conf: PhysicalNetworkConfiguration) extends PhysicalNetworkIO()(data)(conf) {
val temp = UFix(width = conf.idBits)
}
abstract class PhysicalNetworkIO[T <: Data]()(data: => T)(implicit conf: PhysicalNetworkConfiguration) extends FIFOIO()(data) {
val header = (new PhysicalHeader).asInput
}
abstract class PhysicalNetwork(implicit conf: PhysicalNetworkConfiguration) extends Component
class BasicCrossbar[T <: Data]()(data: => T)(implicit conf: PhysicalNetworkConfiguration) extends PhysicalNetwork(conf) {
val io = new Bundle {
val in = Vec(conf.nEndpoints) { (new BasicCrossbarIO) { data } }
val out = Vec(conf.nEndpoints) { (new BasicCrossbarIO) { data } }.flip
}
for(i <- 0 until conf.nEndpoints) {
val rrarb = new RRArbiter(conf.nEndpoints)(data)
(rrarb.io.in, io.in).zipped.map( (arb, io) => {
arb.valid := io.valid && (io.header.dst === UFix(i))
arb.bits := io.bits
io.ready := arb.ready
})
io.out(i) <> rrarb.io.out
}
}
case class LogicalNetworkConfiguration(nEndpoints: Int, idBits: Int)
abstract class LogicalNetwork[TileLinkType <: Bundle](endpoints: Seq[Component])(implicit conf: LogicalNetworkConfiguration) extends Component {
val io: Vec[TileLinkType]
val physicalNetworks: Seq[PhysicalNetwork]
require(endpoints.length == conf.nEndpoints)
}
class LogicalHeader(implicit conf: LogicalNetworkConfiguration) extends Bundle {
val src = UFix(width = conf.idBits)
val dst = UFix(width = conf.idBits)
}
abstract class LogicalNetworkIO[T <: Data]()(data: => T)(implicit m: Manifest[T], conf: LogicalNetworkConfiguration) extends FIFOIO()(data) {
val header = (new LogicalHeader).asInput
}
class TileIO[T <: Data]()(data: => T)(implicit m: Manifest[T], conf: LogicalNetworkConfiguration) extends LogicalNetworkIO()(data)(m,conf)
class HubIO[T <: Data]()(data: => T)(implicit m: Manifest[T], conf: LogicalNetworkConfiguration) extends LogicalNetworkIO()(data)(m,conf)
class TileLink(implicit conf: LogicalNetworkConfiguration) extends Bundle {
val xact_init = (new TileIO) { new TransactionInit }
val xact_init_data = (new TileIO) { new TransactionInitData }
val xact_abort = (new HubIO) { new TransactionAbort }
val probe_req = (new HubIO) { new ProbeRequest }
val probe_rep = (new TileIO) { new ProbeReply }
val probe_rep_data = (new TileIO) { new ProbeReplyData }
val xact_rep = (new HubIO) { new TransactionReply }
val xact_finish = (new TileIO) { new TransactionFinish }
val incoherent = Bool(OUTPUT)
}
class PhysicalAddress extends Bundle { class PhysicalAddress extends Bundle {
val addr = UFix(width = PADDR_BITS - OFFSET_BITS) val addr = UFix(width = PADDR_BITS - OFFSET_BITS)