riscv/rocket-chip
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make BTB fully associative; don't use it for JALR

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JALR created a long path from the ALU in execute stage
to an address comparator to the next-PC mux.  the benfit
was close to nil, anyway.
This commit is contained in:
Andrew Waterman
2012-02-09 01:32:52 -08:00
parent fcc8081c4d
commit 128ec567ed
6 changed files with 57 additions and 41 deletions
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2
rocket/src/main/scala/cpu.scala
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@ -60,7 +60,7 @@ class rocketProc extends Component
io.imem.req_idx := dpath.io.imem.req_addr(PGIDX_BITS-1,0);
io.imem.req_ppn := itlb.io.cpu.resp_ppn;
io.imem.req_val := ctrl.io.imem.req_val;
io.imem.invalidate := ctrl.io.flush_inst;
io.imem.invalidate := ctrl.io.dpath.flush_inst;
ctrl.io.imem.resp_val := io.imem.resp_val;
dpath.io.imem.resp_data := io.imem.resp_data;
ctrl.io.xcpt_itlb := itlb.io.cpu.exception;