riscv/rocket-chip
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Flip direction of some bulk connects

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This commit is contained in:
Andrew Waterman 2015-08-03 18:01:14 -07:00
parent a21979a2fa
commit 121e4fb511
1 changed files with 2 additions and 2 deletions
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4
uncore/src/main/scala/tilelink.scala
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@ -787,7 +787,7 @@ class TileLinkIOWrapper extends TLModule {
val out = new TileLinkIO val out = new TileLinkIO
} }
io.out.acquire <> io.in.acquire io.out.acquire <> io.in.acquire
io.out.grant <> io.in.grant io.in.grant <> io.out.grant
io.out.finish <> io.in.finish io.out.finish <> io.in.finish
io.out.probe.ready := Bool(true) io.out.probe.ready := Bool(true)
io.out.release.valid := Bool(false) io.out.release.valid := Bool(false)
@ -799,7 +799,7 @@ class ClientTileLinkIOWrapper extends TLModule {
val out = new ClientTileLinkIO val out = new ClientTileLinkIO
} }
io.out.acquire <> io.in.acquire io.out.acquire <> io.in.acquire
io.out.grant <> io.in.grant io.in.grant <> io.out.grant
io.out.probe.ready := Bool(true) io.out.probe.ready := Bool(true)
io.out.release.valid := Bool(false) io.out.release.valid := Bool(false)
} }