riscv/rocket-chip
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restore old L2 cache AcquireTransactor configuration

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Howard Mao 2015-11-11 17:10:58 -08:00
parent 31da692ccc
commit 11f0b3d8db
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/Configs.scala
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@ -210,7 +210,7 @@ class WithL2Cache extends Config(
case NWays => Knob("L2_WAYS") case NWays => Knob("L2_WAYS")
case RowBits => site(TLKey(site(TLId))).dataBitsPerBeat case RowBits => site(TLKey(site(TLId))).dataBitsPerBeat
}: PartialFunction[Any,Any] }: PartialFunction[Any,Any]
case NAcquireTransactors => 3 case NAcquireTransactors => 2
case NSecondaryMisses => 4 case NSecondaryMisses => 4
case L2DirectoryRepresentation => new FullRepresentation(site(NTiles)) case L2DirectoryRepresentation => new FullRepresentation(site(NTiles))
case BuildL2CoherenceManager => (p: Parameters) => case BuildL2CoherenceManager => (p: Parameters) =>
@ -266,7 +266,7 @@ class WithMemtest extends Config (
case NGeneratorTiles => 1 case NGeneratorTiles => 1
case NGeneratorsPerTile => 1 case NGeneratorsPerTile => 1
case GenerateUncached => true case GenerateUncached => true
case GenerateCached => true case GenerateCached => false
case MaxGenerateRequests => 8192 case MaxGenerateRequests => 8192
case BuildTiles => { case BuildTiles => {