From 11dbd4221a0dd2af5bbf401069ef7254f773455c Mon Sep 17 00:00:00 2001 From: Christopher Celio Date: Fri, 10 Apr 2015 17:53:47 -0700 Subject: [PATCH] Fixed front-end to support four-wide fetch. --- rocket/src/main/scala/icache.scala | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index d7a820db..b992dd5f 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -114,8 +114,13 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule io.cpu.resp.valid := s2_valid && (s2_xcpt_if || icache.io.resp.valid) io.cpu.resp.bits.pc := s2_pc - - val fetch_data = icache.io.resp.bits.datablock >> (s2_pc(log2Up(rowBytes)-1,log2Up(coreFetchWidth*coreInstBytes)) << log2Up(coreFetchWidth*coreInstBits)) + var fetch_data:Bits = null + require (coreFetchWidth <= 4) + if (coreFetchWidth == 4) { + fetch_data = icache.io.resp.bits.datablock + } else { + fetch_data = icache.io.resp.bits.datablock >> (s2_pc(log2Up(rowBytes)-1,log2Up(coreFetchWidth*coreInstBytes)) << log2Up(coreFetchWidth*coreInstBits)) + } for (i <- 0 until coreFetchWidth) { io.cpu.resp.bits.data(i) := fetch_data(i*coreInstBits+coreInstBits-1, i*coreInstBits) }