Don't re-read I$ RAMs on stall

src/main/scala/rocket/Frontend.scala

@@ -134,7 +134,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
   icache.io.req.valid := !stall && !s0_same_block
   icache.io.req.bits.addr := io.cpu.npc
   icache.io.invalidate := io.cpu.flush_icache
-  icache.io.s1_ppn := tlb.io.resp.ppn
+  icache.io.s1_paddr := Cat(tlb.io.resp.ppn, s1_pc(pgIdxBits-1, 0))
   icache.io.s1_kill := io.cpu.req.valid || tlb.io.resp.miss || tlb.io.resp.xcpt_if || icmiss || io.cpu.flush_tlb
   icache.io.s2_kill := s2_speculative && !s2_cacheable
   icache.io.resp.ready := !stall && !s1_same_block

src/main/scala/rocket/ICache.scala

@@ -44,7 +44,7 @@ class ICache(val latency: Int)(implicit p: Parameters) extends LazyModule {
 
 class ICacheBundle(outer: ICache) extends CoreBundle()(outer.p) {
   val req = Valid(new ICacheReq).flip
-  val s1_ppn = UInt(INPUT, ppnBits) // delayed one cycle w.r.t. req
+  val s1_paddr = UInt(INPUT, paddrBits) // delayed one cycle w.r.t. req
   val s1_kill = Bool(INPUT) // delayed one cycle w.r.t. req
   val s2_kill = Bool(INPUT) // delayed two cycles; prevents I$ miss emission
 
@@ -67,34 +67,27 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
   val state = Reg(init=s_ready)
   val invalidated = Reg(Bool())
   val stall = !io.resp.ready
-  val rdy = Wire(Bool())
 
   val refill_addr = Reg(UInt(width = paddrBits))
   val s1_any_tag_hit = Wire(Bool())
 
   val s1_valid = Reg(init=Bool(false))
-  val s1_vaddr = Reg(UInt())
-  val s1_paddr = Cat(io.s1_ppn, s1_vaddr(pgIdxBits-1,0))
-  val s1_tag = s1_paddr(tagBits+untagBits-1,untagBits)
-
-  val s0_valid = io.req.valid || s1_valid && stall
-  val s0_vaddr = Mux(s1_valid && stall, s1_vaddr, io.req.bits.addr)
-
-  s1_valid := io.req.valid && rdy || s1_valid && stall && !io.s1_kill
-  when (io.req.valid && rdy) {
-    s1_vaddr := io.req.bits.addr
-  }
-
   val out_valid = s1_valid && !io.s1_kill && state === s_ready
-  val s1_idx = s1_vaddr(untagBits-1,blockOffBits)
+  val s1_idx = io.s1_paddr(untagBits-1,blockOffBits)
+  val s1_tag = io.s1_paddr(tagBits+untagBits-1,untagBits)
   val s1_hit = out_valid && s1_any_tag_hit
   val s1_miss = out_valid && !s1_any_tag_hit
-  rdy := state === s_ready && !s1_miss
+
+  val s0_valid = io.req.valid && state === s_ready && !(out_valid && stall)
+  val s0_vaddr = io.req.bits.addr
+
+  s1_valid := s0_valid || out_valid && stall
 
   when (s1_miss && state === s_ready) {
-    refill_addr := s1_paddr
+    refill_addr := io.s1_paddr
   }
   val refill_tag = refill_addr(tagBits+untagBits-1,untagBits)
+  val refill_idx = refill_addr(untagBits-1,blockOffBits)
   val (_, _, refill_done, refill_cnt) = edge.count(tl_out.d)
   tl_out.d.ready := Bool(true)
   require (edge.manager.minLatency > 0)
@@ -105,12 +98,12 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
   val tag_rdata = tag_array.read(s0_vaddr(untagBits-1,blockOffBits), !refill_done && s0_valid)
   when (refill_done) {
     val tag = code.encode(refill_tag)
-    tag_array.write(s1_idx, Vec.fill(nWays)(tag), Vec.tabulate(nWays)(repl_way === _))
+    tag_array.write(refill_idx, Vec.fill(nWays)(tag), Vec.tabulate(nWays)(repl_way === _))
   }
 
   val vb_array = Reg(init=Bits(0, nSets*nWays))
   when (refill_done && !invalidated) {
-    vb_array := vb_array.bitSet(Cat(repl_way, s1_idx), Bool(true))
+    vb_array := vb_array.bitSet(Cat(repl_way, refill_idx), Bool(true))
   }
   when (io.invalidate) {
     vb_array := Bits(0)
@@ -123,12 +116,13 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
   val s1_tag_match = Wire(Vec(nWays, Bool()))
   val s1_tag_hit = Wire(Vec(nWays, Bool()))
   val s1_dout = Wire(Vec(nWays, Bits(width = rowBits)))
+  val s1_dout_valid = RegNext(s0_valid)
 
   for (i <- 0 until nWays) {
-    val s1_vb = !io.invalidate && vb_array(Cat(UInt(i), s1_vaddr(untagBits-1,blockOffBits))).toBool
+    val s1_vb = !io.invalidate && vb_array(Cat(UInt(i), io.s1_paddr(untagBits-1,blockOffBits))).toBool
     val tag_out = tag_rdata(i)
-    val s1_tag_disparity = code.decode(tag_out).error
+    val s1_tag_disparity = code.decode(tag_out).error holdUnless s1_dout_valid
-    s1_tag_match(i) := tag_out(tagBits-1,0) === s1_tag
+    s1_tag_match(i) := (tag_out(tagBits-1,0) === s1_tag) holdUnless s1_dout_valid
     s1_tag_hit(i) := s1_vb && s1_tag_match(i)
     s1_disparity(i) := s1_vb && (s1_tag_disparity || code.decode(s1_dout(i)).error)
   }
@@ -139,10 +133,10 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
     val wen = tl_out.d.valid && repl_way === UInt(i)
     when (wen) {
       val e_d = code.encode(tl_out.d.bits.data)
-      data_array.write((s1_idx << log2Ceil(refillCycles)) | refill_cnt, e_d)
+      data_array.write((refill_idx << log2Ceil(refillCycles)) | refill_cnt, e_d)
     }
     val s0_raddr = s0_vaddr(untagBits-1,blockOffBits-log2Ceil(refillCycles))
-    s1_dout(i) := data_array.read(s0_raddr, !wen && s0_valid)
+    s1_dout(i) := data_array.read(s0_raddr, !wen && s0_valid) holdUnless s1_dout_valid
   }
 
   // output signals