riscv/rocket-chip
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Don't re-read I$ RAMs on stall

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This commit is contained in:
Andrew Waterman
2017-03-05 21:43:20 -08:00
parent db0a02b78e
commit 11c8857b5d
2 changed files with 19 additions and 25 deletions
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2
src/main/scala/rocket/Frontend.scala
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@ -134,7 +134,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
icache.io.req.valid := !stall && !s0_same_block
icache.io.req.bits.addr := io.cpu.npc
icache.io.invalidate := io.cpu.flush_icache
icache.io.s1_ppn := tlb.io.resp.ppn
icache.io.s1_paddr := Cat(tlb.io.resp.ppn, s1_pc(pgIdxBits-1, 0))
icache.io.s1_kill := io.cpu.req.valid || tlb.io.resp.miss || tlb.io.resp.xcpt_if || icmiss || io.cpu.flush_tlb
icache.io.s2_kill := s2_speculative && !s2_cacheable
icache.io.resp.ready := !stall && !s1_same_block