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rocketchip: don't use explicit cde namespace

This commit is contained in:
Wesley W. Terpstra 2016-11-18 12:32:49 -08:00
parent 5bd343bac8
commit 119ccae9af
4 changed files with 6 additions and 5 deletions

View File

@ -22,7 +22,7 @@ object UncoreBuilder extends App {
val gen = () => val gen = () =>
Class.forName(s"uncore.$topModuleName") Class.forName(s"uncore.$topModuleName")
.getConstructor(classOf[cde.Parameters]) .getConstructor(classOf[Parameters])
.newInstance(paramsFromConfig) .newInstance(paramsFromConfig)
.asInstanceOf[Module] .asInstanceOf[Module]

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@ -301,12 +301,12 @@ class DebugBusResp( ) extends Bundle {
* Therefore it has the 'flipped' version of this. * Therefore it has the 'flipped' version of this.
*/ */
class DebugBusIO(implicit val p: cde.Parameters) extends ParameterizedBundle()(p) { class DebugBusIO(implicit val p: Parameters) extends ParameterizedBundle()(p) {
val req = new DecoupledIO(new DebugBusReq(p(DMKey).nDebugBusAddrSize)) val req = new DecoupledIO(new DebugBusReq(p(DMKey).nDebugBusAddrSize))
val resp = new DecoupledIO(new DebugBusResp).flip() val resp = new DecoupledIO(new DebugBusResp).flip()
} }
class AsyncDebugBusIO(implicit val p: cde.Parameters) extends ParameterizedBundle()(p) { class AsyncDebugBusIO(implicit val p: Parameters) extends ParameterizedBundle()(p) {
val req = new AsyncBundle(1, new DebugBusReq(p(DMKey).nDebugBusAddrSize)) val req = new AsyncBundle(1, new DebugBusReq(p(DMKey).nDebugBusAddrSize))
val resp = new AsyncBundle(1, new DebugBusResp).flip val resp = new AsyncBundle(1, new DebugBusResp).flip
} }

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@ -3,8 +3,9 @@
package unittest package unittest
import Chisel._ import Chisel._
import cde._
class TestHarness(implicit val p: cde.Parameters) extends Module { class TestHarness(implicit val p: Parameters) extends Module {
val io = new Bundle { val success = Bool(OUTPUT) } val io = new Bundle { val success = Bool(OUTPUT) }
io.success := Module(new UnitTestSuite).io.finished io.success := Module(new UnitTestSuite).io.finished
} }

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@ -43,7 +43,7 @@ trait HasGeneratorUtilities {
def elaborate(names: ParsedInputNames, params: Parameters): Circuit = { def elaborate(names: ParsedInputNames, params: Parameters): Circuit = {
val gen = () => val gen = () =>
Class.forName(names.fullTopModuleClass) Class.forName(names.fullTopModuleClass)
.getConstructor(classOf[cde.Parameters]) .getConstructor(classOf[Parameters])
.newInstance(params) .newInstance(params)
.asInstanceOf[Module] .asInstanceOf[Module]