riscv/rocket-chip
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Hierarchicalize D$ config

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This commit is contained in:
Andrew Waterman
2016-08-17 16:53:39 -07:00
committed by Howard Mao
parent 3f8c60bbd6
commit 114226252b
5 changed files with 50 additions and 56 deletions
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4
groundtest/src/main/scala/Tile.scala
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@ -107,9 +107,7 @@ class GroundTestTile(resetSignal: Bool)
val memPorts = ListBuffer.empty ++= test.io.mem
if (nCached > 0) {
val dcache_io =
if (p(NMSHRs) == 0) Module(new DCache()(dcacheParams)).io
else Module(new HellaCache()(dcacheParams)).io
val dcache_io = HellaCache(p(DCacheKey))(dcacheParams)
val dcacheArb = Module(new HellaCacheArbiter(nCached)(dcacheParams))
dcacheArb.io.requestor.zip(test.io.cache).foreach {