riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Hierarchicalize D$ config

Browse Source
This commit is contained in:
Andrew Waterman
2016-08-17 16:53:39 -07:00
committed by Howard Mao
parent 3f8c60bbd6
commit 114226252b
5 changed files with 50 additions and 56 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
coreplex/src/main/scala/Configs.scala
View File

@ -62,10 +62,7 @@ class BaseCoreplexConfig extends Config (
//L1InstCache
case BtbKey => BtbParameters()
//L1DataCache
case StoreDataQueueDepth => 17
case ReplayQueueDepth => 16
case NMSHRs => Knob("L1D_MSHRS")
case LRSCCycles => 32
case DCacheKey => DCacheConfig(nMSHRs = site(Knob("L1D_MSHRS")))
//L2 Memory System Params
case AmoAluOperandBits => site(XLen)
case NAcquireTransactors => 7
@ -144,7 +141,7 @@ class BaseCoreplexConfig extends Config (
nCachelessClients = site(NExternalClients) + site(NUncachedTileLinkPorts),
maxClientXacts = max_int(
// L1 cache
site(NMSHRs) + 1 /* IOMSHR */,
site(DCacheKey).nMSHRs + 1 /* IOMSHR */,
// RoCC
if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)),
maxClientsPerPort = if (site(BuildRoCC).isEmpty) 1 else 2,
@ -349,8 +346,6 @@ class WithSmallCores extends Config (
case FPUKey => None
case NTLBEntries => 4
case BtbKey => BtbParameters(nEntries = 0)
case StoreDataQueueDepth => 2
case ReplayQueueDepth => 2
case NAcquireTransactors => 2
case _ => throw new CDEMatchError
}},