From 1134bbf1a4dbc9f479fab240410be8ac0ed1c514 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Sun, 27 Jan 2013 11:59:17 -0800 Subject: [PATCH] cleanup disconnected io pins (overwritten network headers) --- uncore/src/package.scala | 8 +++++--- uncore/src/uncore.scala | 7 +++++++ 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/uncore/src/package.scala b/uncore/src/package.scala index 0e69ff47..46d46661 100644 --- a/uncore/src/package.scala +++ b/uncore/src/package.scala @@ -62,21 +62,23 @@ class LogicalHeader(implicit conf: LogicalNetworkConfiguration) extends Bundle { } object FIFOedLogicalNetworkIOWrapper { - def apply[T <: Data](in: FIFOIO[T])(implicit conf: LogicalNetworkConfiguration) = { - val shim = (new FIFOedLogicalNetworkIOWrapper){ in.bits.clone } + def apply[T <: Data](in: FIFOIO[T], src: UFix = UFix(0), dst: UFix = UFix(0))(implicit conf: LogicalNetworkConfiguration) = { + val shim = (new FIFOedLogicalNetworkIOWrapper(src, dst)){ in.bits.clone } shim.io.in.valid := in.valid shim.io.in.bits := in.bits in.ready := shim.io.in.ready shim.io.out } } -class FIFOedLogicalNetworkIOWrapper[T <: Data]()(data: => T)(implicit lconf: LogicalNetworkConfiguration) extends Component { +class FIFOedLogicalNetworkIOWrapper[T <: Data](src: UFix, dst: UFix)(data: => T)(implicit lconf: LogicalNetworkConfiguration) extends Component { val io = new Bundle { val in = (new FIFOIO){ data }.flip val out = (new FIFOIO){(new LogicalNetworkIO){ data }} } io.out.valid := io.in.valid io.out.bits.payload := io.in.bits + io.out.bits.header.dst := dst + io.out.bits.header.src := src io.in.ready := io.out.ready } diff --git a/uncore/src/uncore.scala b/uncore/src/uncore.scala index 690454a1..01e9c40c 100644 --- a/uncore/src/uncore.scala +++ b/uncore/src/uncore.scala @@ -369,6 +369,8 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co rep.bits.payload.master_xact_id := UFix(0) rep.bits.payload.data := io.mem.resp.bits.data rep.bits.payload.require_ack := Bool(true) + rep.bits.header.dst := UFix(0) // DNC + rep.bits.header.src := UFix(0) // DNC rep.valid := Bool(false) when(io.mem.resp.valid && (UFix(j) === init_client_id_arr(mem_idx))) { rep.bits.payload.g_type := co.getGrantType(a_type_arr(mem_idx), sh_count_arr(mem_idx)) @@ -445,6 +447,8 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co conflicts(i) := t.busy && x_init.valid && co.isCoherenceConflict(t.addr, x_init.bits.payload.addr) } x_abort.bits.payload.client_xact_id := x_init.bits.payload.client_xact_id + x_abort.bits.header.dst := UFix(0) // DNC + x_abort.bits.header.src := UFix(0) // DNC want_to_abort_arr(j) := x_init.valid && (conflicts.toBits.orR || busy_arr.toBits.andR || (!x_init_data_dep_list(j).io.enq.ready && co.messageHasData(x_init.bits.payload))) x_abort.valid := Bool(false) @@ -585,6 +589,7 @@ class L2CoherenceAgent(implicit conf: CoherenceHubConfiguration) extends Coheren // Nack conflicting transaction init attempts x_abort.bits.header.dst := x_init.bits.header.src + x_abort.bits.header.src := UFix(0) //DNC x_abort.bits.payload.client_xact_id := x_init.bits.payload.client_xact_id x_abort.valid := Bool(false) switch(abort_state) { @@ -746,12 +751,14 @@ class XactTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends Com io.p_req.bits.payload.master_xact_id := UFix(id) io.p_req.bits.payload.addr := xact.addr io.p_req.bits.header.dst := UFix(0) + io.p_req.bits.header.src := UFix(0) // DNC io.grant.bits.payload.data := io.mem_resp.bits.data io.grant.bits.payload.g_type := co.getGrantType(xact.a_type, init_sharer_cnt_) io.grant.bits.payload.client_xact_id := xact.client_xact_id io.grant.bits.payload.master_xact_id := UFix(id) io.grant.bits.payload.require_ack := all_grants_require_acks io.grant.bits.header.dst := init_client_id_ + io.grant.bits.header.src := UFix(0) // DNC io.grant.valid := (io.mem_resp.valid && (UFix(id) === io.mem_resp.bits.tag)) io.x_init.ready := Bool(false) io.x_init_data.ready := Bool(false)