rocket: change connection between rocketchip and coreplex

* rtc and dtm are now crossed half-and-half on the two sides
* groundtest no longer uses riscv platform traits

src/main/scala/uncore/devices/Debug.scala

@@ -306,6 +306,31 @@ class DebugBusIO(implicit val p: cde.Parameters) extends ParameterizedBundle()(p
   val resp = new DecoupledIO(new DebugBusResp).flip()
 }
 
+class AsyncDebugBusIO(implicit val p: cde.Parameters) extends ParameterizedBundle()(p) {
+  val req  = new AsyncBundle(1, new DebugBusReq(p(DMKey).nDebugBusAddrSize))
+  val resp = new AsyncBundle(1, new DebugBusResp).flip
+}
+
+object FromAsyncDebugBus
+{
+  def apply(x: AsyncDebugBusIO) = {
+    val out = Wire(new DebugBusIO()(x.p))
+    out.req <> FromAsyncBundle(x.req)
+    x.resp <> ToAsyncBundle(out.resp, 1)
+    out
+  }
+}
+
+object ToAsyncDebugBus
+{
+  def apply(x: DebugBusIO) = {
+    val out = Wire(new AsyncDebugBusIO()(x.p))
+    out.req <> ToAsyncBundle(x.req, 1)
+    x.resp <> FromAsyncBundle(out.resp)
+    out
+  }
+}
+
 trait HasDebugModuleParameters {
   val params : Parameters
   implicit val p = params

src/main/scala/uncore/tilelink2/Bundles.scala

@@ -5,7 +5,7 @@ package uncore.tilelink2
 import Chisel._
 import chisel3.util.{ReadyValidIO}
 import diplomacy._
-import util.{AsyncQueueSource, AsyncQueueSink, GenericParameterizedBundle}
+import util._
 
 abstract class TLBundleBase(params: TLBundleParameters) extends GenericParameterizedBundle(params)
 
@@ -241,58 +241,6 @@ object TLBundleSnoop
   }
 }
 
-final class AsyncBundle[T <: Data](val depth: Int, gen: T) extends Bundle
-{
-  require (isPow2(depth))
-  val mem  = Vec(depth, gen)
-  val ridx = UInt(width = log2Up(depth)+1).flip
-  val widx = UInt(width = log2Up(depth)+1)
-  val ridx_valid = Bool().flip
-  val widx_valid = Bool()
-  val source_reset_n = Bool()
-  val sink_reset_n = Bool().flip
-
-  override def cloneType: this.type = new AsyncBundle(depth, gen).asInstanceOf[this.type]
-}
-
-object FromAsyncBundle
-{
-  def apply[T <: Data](x: AsyncBundle[T], sync: Int = 3): DecoupledIO[T] = {
-    val sink = Module(new AsyncQueueSink(x.mem(0), x.depth, sync))
-    x.ridx := sink.io.ridx
-    x.ridx_valid := sink.io.ridx_valid
-    sink.io.widx := x.widx
-    sink.io.widx_valid := x.widx_valid
-    sink.io.mem  := x.mem
-    sink.io.source_reset_n := x.source_reset_n
-    x.sink_reset_n := !sink.reset
-    val out = Wire(Decoupled(x.mem(0)))
-    out.valid := sink.io.deq.valid
-    out.bits := sink.io.deq.bits
-    sink.io.deq.ready := out.ready
-    out
-  }
-}
-
-object ToAsyncBundle
-{
-  def apply[T <: Data](x: ReadyValidIO[T], depth: Int = 8, sync: Int = 3): AsyncBundle[T] = {
-    val source = Module(new AsyncQueueSource(x.bits, depth, sync))
-    source.io.enq.valid := x.valid
-    source.io.enq.bits := x.bits
-    x.ready := source.io.enq.ready
-    val out = Wire(new AsyncBundle(depth, x.bits))
-    source.io.ridx := out.ridx
-    source.io.ridx_valid := out.ridx_valid
-    out.mem := source.io.mem
-    out.widx := source.io.widx
-    out.widx_valid := source.io.widx_valid
-    source.io.sink_reset_n := out.sink_reset_n
-    out.source_reset_n := !source.reset
-    out
-  }
-}
-
 class TLAsyncBundleBase(params: TLAsyncBundleParameters) extends GenericParameterizedBundle(params)
 
 class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)

src/main/scala/uncore/tilelink2/Isolation.scala

@@ -5,6 +5,7 @@ package uncore.tilelink2
 import Chisel._
 import chisel3.internal.sourceinfo.SourceInfo
 import diplomacy._
+import util.AsyncBundle
 
 // READ the comments in the TLIsolation object before you instantiate this module
 class TLIsolation(fOut: (Bool, UInt) => UInt, fIn: (Bool, UInt) => UInt) extends LazyModule