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rocket: change connection between rocketchip and coreplex

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* rtc and dtm are now crossed half-and-half on the two sides
* groundtest no longer uses riscv platform traits
This commit is contained in:
Wesley W. Terpstra
2016-11-15 18:27:52 -08:00
parent 2d68f12115
commit 10e459fedb
20 changed files with 370 additions and 349 deletions
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13
src/main/scala/rocketchip/DebugTransport.scala
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@ -1,7 +1,7 @@
package rocketchip
import Chisel._
import uncore.devices.{DebugBusIO, AsyncDebugBusCrossing, DebugBusReq, DebugBusResp, DMKey}
import uncore.devices._
import junctions._
import util._
import cde.{Parameters, Field}
@ -45,13 +45,13 @@ class JtagDTMWithSync(depth: Int = 1, sync: Int = 3)(implicit val p: Parameters)
val io = new Bundle {
val jtag = new JTAGIO(true).flip()
val debug = new DebugBusIO()(p)
val jtag = new JTAGIO(true).flip
val debug = new AsyncDebugBusIO
}
val req_width = io.debug.req.bits.getWidth
val resp_width = io.debug.resp.bits.getWidth
val req_width = io.debug.req.mem(0).getWidth
val resp_width = io.debug.resp.mem(0).getWidth
val jtag_dtm = Module (new DebugTransportModuleJtag(req_width, resp_width))
@ -62,7 +62,8 @@ class JtagDTMWithSync(depth: Int = 1, sync: Int = 3)(implicit val p: Parameters)
val io_debug_bus = Wire (new DebugBusIO)
io.debug <> AsyncDebugBusCrossing(io.jtag.TCK, io.jtag.TRST, io_debug_bus, clock, reset, depth, sync)
io.debug.req <> ToAsyncBundle(io_debug_bus.req)
io_debug_bus.resp <> FromAsyncBundle(io.debug.resp)
// Translate from straight 'bits' interface of the blackboxes
// into the Resp/Req data structures.