rocket: change connection between rocketchip and coreplex
* rtc and dtm are now crossed half-and-half on the two sides * groundtest no longer uses riscv platform traits
This commit is contained in:
Wesley W. Terpstra
@ -15,16 +15,13 @@ import coreplex._
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// the following parameters will be refactored properly with TL2
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case object GlobalAddrMap extends Field[AddrMap]
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case object NCoreplexExtClients extends Field[Int]
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/** Enable or disable monitoring of Diplomatic buses */
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case object TLEmitMonitors extends Field[Bool]
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abstract class BareTop[+C <: BaseCoreplex](_coreplex: Parameters => C)(implicit val q: Parameters) extends LazyModule {
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abstract class BareTop[+C <: BaseCoreplex](_coreplex: Parameters => C)(implicit val p: Parameters) extends LazyModule {
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// Fill in the TL1 legacy parameters; remove these once rocket/groundtest/unittest are TL2
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val pBusMasters = new RangeManager
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lazy val legacyAddrMap = GenerateGlobalAddrMap(q, coreplex.l1tol2.node.edgesIn(0).manager.managers)
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val coreplex : C = LazyModule(_coreplex(q.alterPartial {
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case NCoreplexExtClients => pBusMasters.sum
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lazy val legacyAddrMap = GenerateGlobalAddrMap(p, coreplex.l1tol2.node.edgesIn(0).manager.managers)
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val coreplex : C = LazyModule(_coreplex(p.alterPartial {
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case GlobalAddrMap => legacyAddrMap
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}))
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@ -42,8 +39,8 @@ abstract class BareTopModule[+L <: BareTop[BaseCoreplex], +B <: BareTopBundle[L]
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/** Base Top with no Periphery */
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trait TopNetwork extends HasPeripheryParameters {
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this: BareTop[BaseCoreplex] =>
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implicit val p = q
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val module: TopNetworkModule
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TLImp.emitMonitors = p(TLEmitMonitors)
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// Add a SoC and peripheral bus
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@ -60,26 +57,14 @@ trait TopNetwork extends HasPeripheryParameters {
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}
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trait TopNetworkBundle extends HasPeripheryParameters {
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this: BareTopBundle[BareTop[BaseCoreplex]] =>
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implicit val p = outer.q
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val success = Bool(OUTPUT)
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val outer: TopNetwork
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implicit val p = outer.p
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}
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trait TopNetworkModule extends HasPeripheryParameters {
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this: {
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val outer: BareTop[BaseCoreplex] with TopNetwork
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val io: TopNetworkBundle
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} =>
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val io: TopNetworkBundle
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val outer: TopNetwork
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implicit val p = outer.p
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val coreplexSlave: Vec[ClientUncachedTileLinkIO] = Wire(outer.coreplex.module.io.slave)
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val coreplexDebug: DebugBusIO = Wire(outer.coreplex.module.io.debug)
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val coreplexRtc : Bool = Wire(outer.coreplex.module.io.rtcTick)
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io.success := outer.coreplex.module.io.success
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outer.coreplex.module.io.rtcTick := coreplexRtc
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coreplexRtc := Counter(p(rocketchip.RTCPeriod)).inc()
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}
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/** Base Top with no Periphery */
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@ -94,20 +79,11 @@ class BaseTopBundle[+L <: BaseTop[BaseCoreplex]](_outer: L) extends BareTopBundl
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class BaseTopModule[+L <: BaseTop[BaseCoreplex], +B <: BaseTopBundle[L]](_outer: L, _io: () => B) extends BareTopModule(_outer, _io)
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with TopNetworkModule
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trait DirectConnection {
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this: BareTop[BaseCoreplex] with TopNetwork =>
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trait DirectConnection extends TopNetwork {
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val coreplex: BaseCoreplex
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socBus.node := coreplex.mmio
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coreplex.mmioInt := intBus.intnode
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coreplexMem = coreplex.mem
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}
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trait DirectConnectionModule {
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this: TopNetworkModule {
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val outer: BaseTop[BaseCoreplex]
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} =>
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outer.coreplex.module.io.slave <> coreplexSlave
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outer.coreplex.module.io.debug <> coreplexDebug
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}
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@ -62,8 +62,6 @@ class BasePlatformConfig extends Config(
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case TMemoryChannels => BusType.AXI
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case ExtMemSize => Dump("MEM_SIZE", 0x10000000L)
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case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
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case BuildExampleTop =>
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(p: Parameters) => LazyModule(new ExampleTop(new DefaultCoreplex()(_))(p))
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case SimMemLatency => 0
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case _ => throw new CDEMatchError
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}
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@ -1,7 +1,7 @@
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package rocketchip
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import Chisel._
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import uncore.devices.{DebugBusIO, AsyncDebugBusCrossing, DebugBusReq, DebugBusResp, DMKey}
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import uncore.devices._
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import junctions._
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import util._
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import cde.{Parameters, Field}
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@ -45,13 +45,13 @@ class JtagDTMWithSync(depth: Int = 1, sync: Int = 3)(implicit val p: Parameters)
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val io = new Bundle {
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val jtag = new JTAGIO(true).flip()
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val debug = new DebugBusIO()(p)
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val jtag = new JTAGIO(true).flip
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val debug = new AsyncDebugBusIO
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}
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val req_width = io.debug.req.bits.getWidth
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val resp_width = io.debug.resp.bits.getWidth
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val req_width = io.debug.req.mem(0).getWidth
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val resp_width = io.debug.resp.mem(0).getWidth
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val jtag_dtm = Module (new DebugTransportModuleJtag(req_width, resp_width))
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@ -62,7 +62,8 @@ class JtagDTMWithSync(depth: Int = 1, sync: Int = 3)(implicit val p: Parameters)
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val io_debug_bus = Wire (new DebugBusIO)
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io.debug <> AsyncDebugBusCrossing(io.jtag.TCK, io.jtag.TRST, io_debug_bus, clock, reset, depth, sync)
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io.debug.req <> ToAsyncBundle(io_debug_bus.req)
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io_debug_bus.resp <> FromAsyncBundle(io.debug.resp)
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// Translate from straight 'bits' interface of the blackboxes
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// into the Resp/Req data structures.
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@ -12,31 +12,40 @@ import rocketchip._
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class ExampleTop[+C <: BaseCoreplex](_coreplex: Parameters => C)(implicit p: Parameters) extends BaseTop(_coreplex)
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with DirectConnection
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with PeripheryBootROM
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with PeripheryDebug
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with PeripheryExtInterrupts
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with PeripheryMasterAXI4Mem
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with PeripheryMasterAXI4MMIO
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with PeripherySlave {
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with PeripheryMasterAXI4MMIO {
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override lazy val module = new ExampleTopModule(this, () => new ExampleTopBundle(this))
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}
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class ExampleTopBundle[+L <: ExampleTop[BaseCoreplex]](_outer: L) extends BaseTopBundle(_outer)
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with PeripheryBootROMBundle
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with PeripheryDebugBundle
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with PeripheryExtInterruptsBundle
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with PeripheryMasterAXI4MemBundle
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with PeripheryMasterAXI4MMIOBundle
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with PeripherySlaveBundle
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class ExampleTopModule[+L <: ExampleTop[BaseCoreplex], +B <: ExampleTopBundle[L]](_outer: L, _io: () => B) extends BaseTopModule(_outer, _io)
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with DirectConnectionModule
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with PeripheryBootROMModule
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with PeripheryDebugModule
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with PeripheryExtInterruptsModule
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with PeripheryMasterAXI4MemModule
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with PeripheryMasterAXI4MMIOModule
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with PeripherySlaveModule
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with HardwiredResetVector
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class ExampleRocketTop[+C <: DefaultCoreplex](_coreplex: Parameters => C)(implicit p: Parameters) extends ExampleTop(_coreplex)
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with PeripheryDTM
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with PeripheryCounter
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with HardwiredResetVector {
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override lazy val module = new ExampleRocketTopModule(this, () => new ExampleRocketTopBundle(this))
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}
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class ExampleRocketTopBundle[+L <: ExampleRocketTop[DefaultCoreplex]](_outer: L) extends ExampleTopBundle(_outer)
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with PeripheryDTMBundle
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with PeripheryCounterBundle
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with HardwiredResetVectorBundle
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class ExampleRocketTopModule[+L <: ExampleRocketTop[DefaultCoreplex], +B <: ExampleRocketTopBundle[L]](_outer: L, _io: () => B) extends ExampleTopModule(_outer, _io)
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with PeripheryDTMModule
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with PeripheryCounterModule
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with HardwiredResetVectorModule
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/** Example Top with TestRAM */
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class ExampleTopWithTestRAM[+C <: BaseCoreplex](_coreplex: Parameters => C)(implicit p: Parameters) extends ExampleTop(_coreplex)
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@ -92,41 +92,6 @@ trait HasPeripheryParameters {
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/////
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trait PeripheryDebug {
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this: TopNetwork =>
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}
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trait PeripheryDebugBundle {
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this: TopNetworkBundle {
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val outer: PeripheryDebug
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} =>
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val debug_clk = (p(AsyncDebugBus) && !p(IncludeJtagDTM)).option(Clock(INPUT))
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val debug_rst = (p(AsyncDebugBus) && !p(IncludeJtagDTM)).option(Bool(INPUT))
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val debug = (!p(IncludeJtagDTM)).option(new DebugBusIO()(p).flip)
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val jtag = p(IncludeJtagDTM).option(new JTAGIO(true).flip)
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}
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trait PeripheryDebugModule {
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this: TopNetworkModule {
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val outer: PeripheryDebug
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val io: PeripheryDebugBundle
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} =>
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if (p(IncludeJtagDTM)) {
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// JtagDTMWithSync is a wrapper which
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// handles the synchronization as well.
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val dtm = Module (new JtagDTMWithSync()(p))
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dtm.io.jtag <> io.jtag.get
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coreplexDebug <> dtm.io.debug
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} else {
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coreplexDebug <>
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(if (p(AsyncDebugBus)) AsyncDebugBusFrom(io.debug_clk.get, io.debug_rst.get, io.debug.get)
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else io.debug.get)
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}
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}
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/////
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trait PeripheryExtInterrupts {
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this: TopNetwork =>
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@ -238,48 +203,6 @@ trait PeripheryMasterAXI4MMIOModule {
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/////
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trait PeripherySlave {
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this: TopNetwork {
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val pBusMasters: RangeManager
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} =>
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if (p(NExtBusAXIChannels) > 0) pBusMasters.add("ext", 1) // NExtBusAXIChannels are arbitrated into one TL port
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}
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trait PeripherySlaveBundle {
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this: TopNetworkBundle {
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val outer: PeripherySlave
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} =>
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val bus_clk = p(AsyncBusChannels).option(Vec(p(NExtBusAXIChannels), Clock(INPUT)))
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val bus_rst = p(AsyncBusChannels).option(Vec(p(NExtBusAXIChannels), Bool (INPUT)))
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val bus_axi = Vec(p(NExtBusAXIChannels), new NastiIO).flip
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}
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trait PeripherySlaveModule {
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this: TopNetworkModule {
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val outer: PeripherySlave { val pBusMasters: RangeManager }
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val io: PeripherySlaveBundle
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} =>
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if (p(NExtBusAXIChannels) > 0) {
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val arb = Module(new NastiArbiter(p(NExtBusAXIChannels)))
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((io.bus_axi zip arb.io.master) zipWithIndex) foreach { case ((bus, port), idx) =>
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port <> (
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if (!p(AsyncBusChannels)) bus
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else AsyncNastiFrom(io.bus_clk.get(idx), io.bus_rst.get(idx), bus)
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)
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}
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val conv = Module(new TileLinkIONastiIOConverter()(edgeSlaveParams))
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conv.io.nasti <> arb.io.slave
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val (r_start, r_end) = outer.pBusMasters.range("ext")
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require(r_end - r_start == 1, "RangeManager should return 1 slot")
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TileLinkWidthAdapter(coreplexSlave(r_start), conv.io.tl)
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}
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}
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/////
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trait PeripheryBootROM {
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this: TopNetwork =>
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@ -344,12 +267,3 @@ trait PeripheryTestBusMasterModule {
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val io: PeripheryTestBusMasterBundle
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} =>
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}
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/////
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trait HardwiredResetVector {
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this: TopNetworkModule {
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val outer: BaseTop[BaseCoreplex]
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} =>
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outer.coreplex.module.io.resetVector := UInt(0x1000) // boot ROM
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}
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92
src/main/scala/rocketchip/RISCVPlatform.scala
Normal file
92
src/main/scala/rocketchip/RISCVPlatform.scala
Normal file
@ -0,0 +1,92 @@
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// See LICENSE for license details.
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package rocketchip
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import Chisel._
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import cde.{Parameters, Field, Dump}
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import diplomacy._
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import uncore.tilelink2._
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import uncore.devices._
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import util._
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import junctions.JTAGIO
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import coreplex._
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trait PeripheryJTAG extends TopNetwork {
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val module: PeripheryJTAGModule
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val coreplex: CoreplexRISCVPlatform
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}
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trait PeripheryJTAGBundle extends TopNetworkBundle {
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val outer: PeripheryJTAG
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val jtag = new JTAGIO(true).flip
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}
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trait PeripheryJTAGModule extends TopNetworkModule {
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val outer: PeripheryJTAG
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val io: PeripheryJTAGBundle
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val dtm = Module (new JtagDTMWithSync)
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dtm.io.jtag <> io.jtag
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outer.coreplex.module.io.debug <> dtm.io.debug
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dtm.clock := io.jtag.TCK
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dtm.reset := io.jtag.TRST
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}
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trait PeripheryDTM extends TopNetwork {
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val module: PeripheryDTMModule
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val coreplex: CoreplexRISCVPlatform
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}
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trait PeripheryDTMBundle extends TopNetworkBundle {
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val outer: PeripheryDTM
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val debug = new DebugBusIO().flip
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}
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trait PeripheryDTMModule extends TopNetworkModule {
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val outer: PeripheryDTM
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val io: PeripheryDTMBundle
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outer.coreplex.module.io.debug <> ToAsyncDebugBus(io.debug)
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}
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trait PeripheryCounter extends TopNetwork {
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val module: PeripheryCounterModule
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val coreplex: CoreplexRISCVPlatform
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}
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trait PeripheryCounterBundle extends TopNetworkBundle {
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val outer: PeripheryCounter
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}
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trait PeripheryCounterModule extends TopNetworkModule {
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val outer: PeripheryCounter
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val io: PeripheryCounterBundle
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{
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val period = p(rocketchip.RTCPeriod)
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val rtcCounter = RegInit(UInt(0, width = log2Up(period)))
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val rtcWrap = rtcCounter === UInt(period-1)
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rtcCounter := Mux(rtcWrap, UInt(0), rtcCounter + UInt(1))
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outer.coreplex.module.io.rtcToggle := rtcCounter(log2Up(period)-1)
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}
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}
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trait HardwiredResetVector extends TopNetwork {
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val module: HardwiredResetVectorModule
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val coreplex: CoreplexRISCVPlatform
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}
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trait HardwiredResetVectorBundle extends TopNetworkBundle {
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val outer: HardwiredResetVector
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}
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trait HardwiredResetVectorModule extends TopNetworkModule {
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val outer: HardwiredResetVector
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val io: HardwiredResetVectorBundle
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outer.coreplex.module.io.resetVector := UInt(0x1000) // boot ROM
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}
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@ -5,6 +5,8 @@ package rocketchip
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import Chisel._
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import cde.{Parameters, Field}
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import junctions._
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import diplomacy._
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import coreplex._
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import junctions.NastiConstants._
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import util.LatencyPipe
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@ -15,12 +17,8 @@ class TestHarness(q: Parameters) extends Module {
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val io = new Bundle {
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val success = Bool(OUTPUT)
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}
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val dut = Module(q(BuildExampleTop)(q).module)
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implicit val p = dut.p
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// This test harness isn't especially flexible yet
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require(dut.io.bus_clk.isEmpty)
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require(dut.io.bus_rst.isEmpty)
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implicit val p = q
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val dut = Module(LazyModule(new ExampleRocketTop(new DefaultCoreplex()(_))).module)
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for (int <- dut.io.interrupts(0))
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int := Bool(false)
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@ -38,26 +36,7 @@ class TestHarness(q: Parameters) extends Module {
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}
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}
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if (!p(IncludeJtagDTM)) {
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// Todo: enable the usage of different clocks
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// to test the synchronizer more aggressively.
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val dtm_clock = clock
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val dtm_reset = reset
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if (dut.io.debug_clk.isDefined) dut.io.debug_clk.get := dtm_clock
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if (dut.io.debug_rst.isDefined) dut.io.debug_rst.get := dtm_reset
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val dtm = Module(new SimDTM).connect(dtm_clock, dtm_reset, dut.io.debug.get,
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dut.io.success, io.success)
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} else {
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val jtag = Module(new JTAGVPI).connect(dut.io.jtag.get, reset, io.success)
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}
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for (bus_axi <- dut.io.bus_axi) {
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bus_axi.ar.valid := Bool(false)
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bus_axi.aw.valid := Bool(false)
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bus_axi.w.valid := Bool(false)
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bus_axi.r.ready := Bool(false)
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bus_axi.b.ready := Bool(false)
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}
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val dtm = Module(new SimDTM).connect(clock, reset, dut.io.debug, io.success)
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for (mmio_axi <- dut.io.mmio_axi) {
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val slave = Module(new NastiErrorSlave)
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@ -128,13 +107,12 @@ class SimDTM(implicit p: Parameters) extends BlackBox {
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val exit = UInt(OUTPUT, 32)
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}
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def connect(tbclk: Clock, tbreset: Bool, dutio: uncore.devices.DebugBusIO,
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dutsuccess: Bool, tbsuccess: Bool) = {
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def connect(tbclk: Clock, tbreset: Bool, dutio: uncore.devices.DebugBusIO, tbsuccess: Bool) = {
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io.clk := tbclk
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io.reset := tbreset
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dutio <> io.debug
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tbsuccess := dutsuccess || io.exit === UInt(1)
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tbsuccess := io.exit === UInt(1)
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when (io.exit >= UInt(2)) {
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printf("*** FAILED *** (exit code = %d)\n", io.exit >> UInt(1))
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stop(1)
|
||||
|
||||
Reference in New Issue
Block a user