rocket: change connection between rocketchip and coreplex

* rtc and dtm are now crossed half-and-half on the two sides
* groundtest no longer uses riscv platform traits

src/main/scala/rocket/tile.scala

@@ -43,7 +43,7 @@ class RocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule {
   val cachedOut = TLOutputNode()
   val uncachedOut = TLOutputNode()
   cachedOut := dcache.node
-  uncachedOut := ucLegacy.node
+  uncachedOut := TLHintHandler()(ucLegacy.node)
   val masterNodes = List(cachedOut, uncachedOut)
   
   (slaveNode zip scratch) foreach { case (node, lm) => lm.node := TLFragmenter(p(XLen)/8, p(CacheBlockBytes))(node) }