rocket: change connection between rocketchip and coreplex

* rtc and dtm are now crossed half-and-half on the two sides
* groundtest no longer uses riscv platform traits

src/main/scala/groundtest/Configs.scala

@@ -81,7 +81,7 @@ class WithGroundTest extends Config(
           else new MESICoherence(site(L2DirectoryRepresentation))),
         nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1,
         nCachingClients = 1,
-        nCachelessClients = site(NCoreplexExtClients) + 1,
+        nCachelessClients = 1,
         maxClientXacts = ((site(DCacheKey).nMSHRs + 1) +:
                            site(GroundTestKey).map(_.maxXacts))
                              .reduce(max(_, _)),

src/main/scala/groundtest/Coreplex.scala

@@ -9,9 +9,8 @@ import rocket.TileId
 import uncore.tilelink.TLId
 
 class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex
-    with BroadcastL2
-    with DirectConnection {
-  val tiles = (0 until p(NTiles)).map { i =>
+    with BroadcastL2 {
+  val tiles = List.tabulate(p(NTiles)) { i =>
     LazyModule(new GroundTestTile()(p.alterPartial({
       case TLId => "L1toL2"
       case TileId => i
@@ -21,8 +20,10 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex
 }
 
 class GroundTestCoreplexBundle[+L <: GroundTestCoreplex](_outer: L) extends BaseCoreplexBundle(_outer)
-
-class GroundTestCoreplexModule[+L <: GroundTestCoreplex, +B <: GroundTestCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io)
-    with DirectConnectionModule {
-  io.success := outer.tiles.flatMap(_.module.io.elements get "success").map(_.asInstanceOf[Bool]).reduce(_&&_)
+{
+  val success = Bool(OUTPUT)
+}
+
+class GroundTestCoreplexModule[+L <: GroundTestCoreplex, +B <: GroundTestCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io) {
+  io.success := outer.tiles.map(_.module.io.success).reduce(_&&_)
 }