rocket: change connection between rocketchip and coreplex

* rtc and dtm are now crossed half-and-half on the two sides
* groundtest no longer uses riscv platform traits

src/main/scala/coreplex/RISCVPlatform.scala

@@ -0,0 +1,73 @@
+package coreplex
+
+import Chisel._
+import cde.{Parameters, Field}
+import junctions._
+import diplomacy._
+import uncore.tilelink._
+import uncore.tilelink2._
+import uncore.coherence._
+import uncore.agents._
+import uncore.devices._
+import uncore.util._
+import uncore.converters._
+import rocket._
+import util._
+
+trait CoreplexRISCVPlatform extends CoreplexNetwork {
+  val module: CoreplexRISCVPlatformModule
+
+  val debug = LazyModule(new TLDebugModule())
+  val plic  = LazyModule(new TLPLIC(hasSupervisor, maxPriorities = 7))
+  val clint = LazyModule(new CoreplexLocalInterrupter)
+
+  debug.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
+  plic.node  := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
+  clint.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
+
+  plic.intnode := mmioInt
+
+}
+
+trait CoreplexRISCVPlatformBundle extends CoreplexNetworkBundle {
+  val outer: CoreplexRISCVPlatform
+
+  val debug = new AsyncDebugBusIO().flip
+  val rtcToggle = Bool(INPUT)
+  val resetVector = UInt(INPUT, p(XLen))
+}
+
+trait CoreplexRISCVPlatformModule extends CoreplexNetworkModule {
+  val outer: CoreplexRISCVPlatform
+  val io: CoreplexRISCVPlatformBundle
+
+  // Synchronize the debug bus into the coreplex
+  outer.debug.module.io.db <> FromAsyncDebugBus(io.debug)
+
+  // Synchronize the rtc into the coreplex
+  val rtcSync = ShiftRegister(io.rtcToggle, 3)
+  val rtcLast = Reg(init = Bool(false), next=rtcSync)
+  outer.clint.module.io.rtcTick := Reg(init = Bool(false), next=(rtcSync & (~rtcLast)))
+
+  println("\nGenerated Address Map")
+  for (entry <- p(rocketchip.GlobalAddrMap).flatten) {
+    val name = entry.name
+    val start = entry.region.start
+    val end = entry.region.start + entry.region.size - 1
+    val prot = entry.region.attr.prot
+    val protStr = (if ((prot & AddrMapProt.R) > 0) "R" else "") +
+                  (if ((prot & AddrMapProt.W) > 0) "W" else "") +
+                  (if ((prot & AddrMapProt.X) > 0) "X" else "")
+    val cacheable = if (entry.region.attr.cacheable) " [C]" else ""
+    println(f"\t$name%s $start%x - $end%x, $protStr$cacheable")
+  }
+
+  // Create and export the ConfigString
+  val managers = outer.l1tol2.node.edgesIn(0).manager.managers
+  val configString = rocketchip.GenerateConfigString(p, outer.clint, outer.plic, managers)
+  // Allow something else to have override the config string
+  if (!ConfigStringOutput.contents.isDefined) {
+    ConfigStringOutput.contents = Some(configString)
+  }
+  println(s"\nGenerated Configuration String\n${ConfigStringOutput.contents.get}")
+}