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rocket: change connection between rocketchip and coreplex

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* rtc and dtm are now crossed half-and-half on the two sides
* groundtest no longer uses riscv platform traits
This commit is contained in:
Wesley W. Terpstra
2016-11-15 18:27:52 -08:00
parent 2d68f12115
commit 10e459fedb
20 changed files with 370 additions and 349 deletions
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4
src/main/scala/coreplex/Configs.scala
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@ -13,7 +13,7 @@ import uncore.converters._
import rocket._
import util._
import util.ConfigUtils._
import rocketchip.{GlobalAddrMap, NCoreplexExtClients}
import rocketchip.{GlobalAddrMap}
import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
class BaseCoreplexConfig extends Config (
@ -104,7 +104,7 @@ class BaseCoreplexConfig extends Config (
else new MESICoherence(site(L2DirectoryRepresentation))),
nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1 /* MMIO */,
nCachingClients = 1,
nCachelessClients = site(NCoreplexExtClients) + 1,
nCachelessClients = 1,
maxClientXacts = max_int(
// L1 cache
site(DCacheKey).nMSHRs + 1 /* IOMSHR */,