From 10d084b9f3461b54bbed4396317d2628b6dc5764 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Wed, 26 Oct 2016 11:23:52 -0700 Subject: [PATCH] DebugModule: Use the power of RegisterRouter to simplify the DebugROM code. --- src/main/scala/uncore/devices/Debug.scala | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/src/main/scala/uncore/devices/Debug.scala b/src/main/scala/uncore/devices/Debug.scala index cae84406..e5cd0af6 100644 --- a/src/main/scala/uncore/devices/Debug.scala +++ b/src/main/scala/uncore/devices/Debug.scala @@ -789,20 +789,11 @@ trait DebugModule extends Module with HasDebugModuleParameters with HasRegMap { //-------------------------------------------------------------- val romRegFields = if (cfg.hasDebugRom) { - // Inspired by ROMSlave - val romContents = cfg.debugRomContents.get - val romByteWidth = ramDataWidth / 8 - val romRows = (romContents.size + romByteWidth - 1)/romByteWidth - List.tabulate(romRows) { ii => { - val slice = romContents.slice(ii*romByteWidth, (ii+1)*romByteWidth) - val line = UInt(slice.foldRight(BigInt(0)) { case (x,y) => ((y << 8) + (x.toInt & 0xFF))}, width = romByteWidth*8) - RegField.r(ramDataWidth, line) - } - } + cfg.debugRomContents.get.map( x => RegField.r(8, UInt(x.toInt & 0xFF))) } else { - Seq(RegField(ramDataWidth)) + Seq(RegField(8)) } - + //-------------------------------------------------------------- // System Bus Access //--------------------------------------------------------------