riscv/rocket-chip
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Disable mprv in D-mode

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This commit is contained in:
Andrew Waterman 2017-03-22 17:18:04 -07:00
parent d3bda9574c
commit 10c39cb8d6
1 changed files with 1 additions and 1 deletions
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src/main/scala/rocket/CSR.scala
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@ -467,7 +467,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
io.status.isa := reg_misa io.status.isa := reg_misa
io.status.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0) io.status.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0)
io.status.sxl := (if (usingVM) log2Ceil(xLen) - 4 else 0) io.status.sxl := (if (usingVM) log2Ceil(xLen) - 4 else 0)
io.status.dprv := Reg(next = Mux(reg_mstatus.mprv, reg_mstatus.mpp, reg_mstatus.prv)) io.status.dprv := Reg(next = Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpp, reg_mstatus.prv))
if (xLen == 32) if (xLen == 32)
io.status.sd_rv32 := io.status.sd io.status.sd_rv32 := io.status.sd