From 10a6a42a4acd6bf1b3ec6c3c9a7ef30cf2be40d9 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@eecs.berkeley.edu>
Date: Thu, 6 Dec 2012 03:13:45 -0800
Subject: [PATCH] make vlsi use dram model by default

---
 riscv-rocket | 2 +-
 uncore       | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/riscv-rocket b/riscv-rocket
index b035b238..8c1b05f6 160000
--- a/riscv-rocket
+++ b/riscv-rocket
@@ -1 +1 @@
-Subproject commit b035b2385282db65c0e700bb4b5136dc3ebcda5d
+Subproject commit 8c1b05f604e562d95e9ffeee57c570720cd16702
diff --git a/uncore b/uncore
index 5cfbf2bc..bbe2066a 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit 5cfbf2bce844b3fec7dd3446dbf15960aba7cb55
+Subproject commit bbe2066a56cac3400611ba86f1cd4395e900c278