From 1054cec0871b8a14f5fd6111330905e5e63f38cf Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Fri, 2 Mar 2012 00:43:32 -0800 Subject: [PATCH] add vec countq interface --- rocket/src/main/scala/consts.scala | 5 +++-- rocket/src/main/scala/cpu.scala | 1 + rocket/src/main/scala/ctrl_vec.scala | 4 +++- rocket/src/main/scala/dpath.scala | 3 +++ rocket/src/main/scala/dpath_util.scala | 4 ++-- rocket/src/main/scala/dpath_vec.scala | 6 ++++++ 6 files changed, 18 insertions(+), 5 deletions(-) diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala index e173aca2..f0c2432a 100644 --- a/rocket/src/main/scala/consts.scala +++ b/rocket/src/main/scala/consts.scala @@ -144,8 +144,9 @@ object Constants val PCR_VECBANK = UFix(18, 5); // temporaries for vector, these will go away - val PCR_VEC_TMP1 = UFix(30, 5) - val PCR_VEC_TMP2 = UFix(31, 5) + val PCR_VEC_CNT = UFix(29, 5) + val PCR_VEC_EADDR = UFix(30, 5) + val PCR_VEC_XCPT = UFix(31, 5) // definition of bits in PCR status reg val SR_ET = 0; // enable traps diff --git a/rocket/src/main/scala/cpu.scala b/rocket/src/main/scala/cpu.scala index b6d1a9e2..06d27ca4 100644 --- a/rocket/src/main/scala/cpu.scala +++ b/rocket/src/main/scala/cpu.scala @@ -169,6 +169,7 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal) vu.io.vec_ximm1q.bits := dpath.io.vec_iface.vximm1q_bits vu.io.vec_ximm2q.valid := ctrl.io.vec_iface.vximm2q_valid vu.io.vec_ximm2q.bits := dpath.io.vec_iface.vximm2q_bits + vu.io.vec_cntq <> dpath.io.vec_iface.vcntq // prefetch queues vu.io.vec_pfcmdq.valid := ctrl.io.vec_iface.vpfcmdq_valid diff --git a/rocket/src/main/scala/ctrl_vec.scala b/rocket/src/main/scala/ctrl_vec.scala index 8ca0ce68..835478ec 100644 --- a/rocket/src/main/scala/ctrl_vec.scala +++ b/rocket/src/main/scala/ctrl_vec.scala @@ -10,6 +10,7 @@ class ioCtrlDpathVec extends Bundle val valid = Bool(INPUT) val inst = Bits(32, INPUT) val appvl0 = Bool(INPUT) + val replay_cntq = Bool(INPUT) val wen = Bool(OUTPUT) val fn = Bits(1, OUTPUT) val sel_vcmd = Bits(3, OUTPUT) @@ -160,7 +161,8 @@ class rocketCtrlVec extends Component wb_vec_ximm2q_enq && !io.iface.vximm2q_ready || wb_vec_pfcmdq_enq && !io.iface.vpfcmdq_ready || wb_vec_pfximm1q_enq && !io.iface.vpfximm1q_ready || - wb_vec_pfximm2q_enq && !io.iface.vpfximm2q_ready + wb_vec_pfximm2q_enq && !io.iface.vpfximm2q_ready || + io.dpath.replay_cntq ) val reg_cpfence = Reg(resetVal = Bool(false)) diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala index 817e001b..a09a3f26 100644 --- a/rocket/src/main/scala/dpath.scala +++ b/rocket/src/main/scala/dpath.scala @@ -385,6 +385,9 @@ class rocketDpath extends Component vec.io.rs2 := wb_reg_rs2 vec.io.vec_eaddr := pcr.io.vec_eaddr vec.io.vec_exception := pcr.io.vec_exception + vec.io.pcr_wport.addr := wb_reg_raddr2 + vec.io.pcr_wport.en := io.ctrl.wen_pcr + vec.io.pcr_wport.data := wb_reg_wdata wb_wdata := Mux(vec.io.wen, Cat(Bits(0,52), vec.io.appvl), diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala index 269029f4..6afc8a8e 100644 --- a/rocket/src/main/scala/dpath_util.scala +++ b/rocket/src/main/scala/dpath_util.scala @@ -211,8 +211,8 @@ class rocketDpathPCR extends Component when (waddr === PCR_K1) { reg_k1 := wdata; } when (waddr === PCR_PTBR) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUFix; } when (waddr === PCR_VECBANK) { reg_vecbank := wdata(7,0) } - when (waddr === PCR_VEC_TMP1) { reg_vec_eaddr := wdata(VADDR_BITS,0) } - when (waddr === PCR_VEC_TMP2) { reg_vec_exception:= wdata(0) } + when (waddr === PCR_VEC_EADDR) { reg_vec_eaddr := wdata(VADDR_BITS,0) } + when (waddr === PCR_VEC_XCPT) { reg_vec_exception:= wdata(0) } } rdata := Bits(0, 64) diff --git a/rocket/src/main/scala/dpath_vec.scala b/rocket/src/main/scala/dpath_vec.scala index ddb629ff..f801ac5c 100644 --- a/rocket/src/main/scala/dpath_vec.scala +++ b/rocket/src/main/scala/dpath_vec.scala @@ -11,6 +11,7 @@ class ioDpathVecInterface extends Bundle val vcmdq_bits = Bits(SZ_VCMD, OUTPUT) val vximm1q_bits = Bits(SZ_VIMM, OUTPUT) val vximm2q_bits = Bits(SZ_VSTRIDE, OUTPUT) + val vcntq = (new ioDecoupled()){ Bits(width = 11) } val eaddr = Bits(64, OUTPUT) val exception = Bool(OUTPUT) } @@ -29,6 +30,7 @@ class ioDpathVec extends Bundle val rs2 = Bits(64, INPUT) val vec_eaddr = Bits(64, INPUT) val vec_exception = Bool(INPUT) + val pcr_wport = new ioWritePort() val wen = Bool(OUTPUT) val appvl = UFix(12, OUTPUT) } @@ -129,6 +131,10 @@ class rocketDpathVec extends Component io.iface.vximm2q_bits := io.rs2 + io.iface.vcntq.bits := io.pcr_wport.data + io.iface.vcntq.valid := io.pcr_wport.en && io.pcr_wport.addr === PCR_VEC_CNT + io.ctrl.replay_cntq := io.iface.vcntq.valid && !io.iface.vcntq.ready + io.iface.eaddr := io.vec_eaddr io.iface.exception := io.vec_exception