[tracegen] remove TL1 noisemaker, use io.finish and catch simulation exit (#528)

scripts/tracegen.py

@@ -52,7 +52,9 @@ def main():
       numFinished = numFinished + 1
       if numFinished == total:
         break
-    elif line[0:12] == "using random":
+    elif line[0:15] == "Completed after":
+      break
+    elif line[0:7] == "testing":
       continue
     else:
       print line,

src/main/scala/groundtest/Configs.scala

@@ -149,7 +149,7 @@ class WithCacheRegressionTest extends Config((site, here, up) => {
 
 class WithTraceGen extends Config((site, here, up) => {
   case GroundTestKey => Seq.fill(site(NTiles)) {
-    GroundTestTileSettings(uncached = 1, cached = 1)
+    GroundTestTileSettings(uncached = 0, cached = 1)
   }
   case BuildGroundTest =>
     (p: Parameters) => Module(new GroundTestTraceGenerator()(p))

src/main/scala/groundtest/TraceGen.scala

@@ -559,68 +559,10 @@ class TraceGenerator(id: Int)
     printf(s"FINISHED ${numGens}\n")
   }
 
-  io.finished := Bool(false)
+  io.finished := done
   io.timeout := reqTimer.io.timeout.valid
 }
 
-class NoiseGenerator(implicit val p: Parameters) extends Module
-    with HasTraceGenParams
-    with HasTileLinkParameters
-    with HasGroundTestParameters {
-  val io = new Bundle {
-    val mem = new ClientUncachedTileLinkIO
-    val finished = Bool(INPUT)
-  }
-
-  val idBits = tlClientXactIdBits
-  val xact_id_free = Reg(UInt(width = idBits), init = ~UInt(0, idBits))
-  val xact_id_onehot = PriorityEncoderOH(xact_id_free)
-
-  val timer = Module(new DynamicTimer(8))
-  timer.io.start := io.mem.acquire.fire()
-  timer.io.period := LCG(8, io.mem.acquire.fire())
-  timer.io.stop := Bool(false)
-
-  val s_start :: s_send :: s_wait :: s_done :: Nil = Enum(Bits(), 4)
-  val state = Reg(init = s_start)
-
-  when (state === s_start) { state := s_send }
-  when (io.mem.acquire.fire()) { state := s_wait }
-  when (state === s_wait) {
-    when (timer.io.timeout) { state := s_send }
-    when (io.finished) { state := s_done }
-  }
-
-  val acq_id = OHToUInt(xact_id_onehot)
-  val gnt_id = io.mem.grant.bits.client_xact_id
-
-  xact_id_free := (xact_id_free &
-                    ~Mux(io.mem.acquire.fire(), xact_id_onehot, UInt(0))) |
-                    Mux(io.mem.grant.fire(), UIntToOH(gnt_id), UInt(0))
-
-  val tlBlockOffset = tlBeatAddrBits + tlByteAddrBits
-  val addr_idx = LCG(logAddressBagLen, io.mem.acquire.fire())
-  val addr_bag = Vec(addressBag.map(
-    addr => UInt(memStartBlock + (addr >> tlBlockOffset), tlBlockAddrBits)))
-  val addr_block = addr_bag(addr_idx)
-  val addr_beat = LCG(tlBeatAddrBits, io.mem.acquire.fire())
-  val acq_select = LCG(1, io.mem.acquire.fire())
-
-  val get_acquire = Get(
-    client_xact_id = acq_id,
-    addr_block = addr_block,
-    addr_beat = addr_beat)
-  val put_acquire = Put(
-    client_xact_id = acq_id,
-    addr_block = addr_block,
-    addr_beat = addr_beat,
-    data = UInt(0),
-    wmask = Some(UInt(0)))
-
-  io.mem.acquire.valid := (state === s_send) && xact_id_free.orR
-  io.mem.acquire.bits := Mux(acq_select(0), get_acquire, put_acquire)
-  io.mem.grant.ready := !xact_id_free(gnt_id)
-}
 
 // =======================
 // Trace-generator wrapper
@@ -635,12 +577,6 @@ class GroundTestTraceGenerator(implicit p: Parameters)
   val traceGen = Module(new TraceGenerator(p(TileId)))
   io.cache.head <> traceGen.io.mem
 
-  if (io.mem.size == 1) {
-    val noiseGen = Module(new NoiseGenerator)
-    io.mem.head <> noiseGen.io.mem
-    noiseGen.io.finished := traceGen.io.finished
-  }
-
   io.status.finished := traceGen.io.finished
   io.status.timeout.valid := traceGen.io.timeout
   io.status.timeout.bits := UInt(0)