From 6b79842e66d006cab055820563c226c3ba559435 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Thu, 15 Jun 2017 18:09:23 -0700 Subject: [PATCH 1/5] dcache: just left shift by untagbits to get tag Always safe because of the requirement on coreplex/RocketTiles.scala:126 --- src/main/scala/rocket/DCache.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala index 1b81ec5f..19d9d5d7 100644 --- a/src/main/scala/rocket/DCache.scala +++ b/src/main/scala/rocket/DCache.scala @@ -134,7 +134,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { when (s1_valid && s1_readwrite && tlb.io.resp.miss) { s1_nack := true } val s1_paddr = tlb.io.resp.paddr - val s1_tag = Mux(s1_probe, probe_bits.address, s1_paddr)(paddrBits-1, untagBits) + val s1_tag = Mux(s1_probe, probe_bits.address, s1_paddr) >> untagBits val s1_victim_way = Wire(init = replacer.way) val (s1_hit_way, s1_hit_state, s1_victim_meta) = if (usingDataScratchpad) { @@ -275,7 +275,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { metaWriteArb.io.in(0).bits.way_en := s2_victim_way metaWriteArb.io.in(0).bits.idx := s2_req.addr(idxMSB, idxLSB) metaWriteArb.io.in(0).bits.data.coh := Mux(s2_valid_hit, s2_new_hit_state, ClientMetadata.onReset) - metaWriteArb.io.in(0).bits.data.tag := s2_req.addr(paddrBits-1, untagBits) + metaWriteArb.io.in(0).bits.data.tag := s2_req.addr >> untagBits // Prepare a TileLink request message that initiates a transaction val a_source = PriorityEncoder(~uncachedInFlight.asUInt << mmioOffset) // skip the MSHR @@ -385,7 +385,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { metaWriteArb.io.in(1).bits.way_en := s2_victim_way metaWriteArb.io.in(1).bits.idx := s2_req.addr(idxMSB, idxLSB) metaWriteArb.io.in(1).bits.data.coh := s2_hit_state.onGrant(s2_req.cmd, tl_out.d.bits.param) - metaWriteArb.io.in(1).bits.data.tag := s2_req.addr(paddrBits-1, untagBits) + metaWriteArb.io.in(1).bits.data.tag := s2_req.addr >> untagBits // don't accept uncached grants if there's a structural hazard on s2_data... val blockUncachedGrant = Reg(Bool()) blockUncachedGrant := dataArb.io.out.valid @@ -489,7 +489,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { metaWriteArb.io.in(2).bits.way_en := releaseWay metaWriteArb.io.in(2).bits.idx := tl_out.c.bits.address(idxMSB, idxLSB) metaWriteArb.io.in(2).bits.data.coh := newCoh - metaWriteArb.io.in(2).bits.data.tag := tl_out.c.bits.address(paddrBits-1, untagBits) + metaWriteArb.io.in(2).bits.data.tag := tl_out.c.bits.address >> untagBits when (metaWriteArb.io.in(2).fire()) { release_state := s_ready } // cached response From 5552f2329425f771f9c916295b03346bbf2ba7e1 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Fri, 16 Jun 2017 12:55:59 -0700 Subject: [PATCH 2/5] tims: explictly name them for generated address map --- src/main/scala/rocket/ICache.scala | 2 ++ src/main/scala/rocket/ScratchpadSlavePort.scala | 2 +- src/main/scala/uncore/tilelink2/SRAM.scala | 5 ++--- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala index b4bb7aa2..cd4bed4d 100644 --- a/src/main/scala/rocket/ICache.scala +++ b/src/main/scala/rocket/ICache.scala @@ -40,11 +40,13 @@ class ICache(val icacheParams: ICacheParams, val hartid: Int)(implicit p: Parame val masterNode = TLClientNode(TLClientParameters(name = s"Core ${hartid} ICache")) val size = icacheParams.nSets * icacheParams.nWays * icacheParams.blockBytes + val device = new SimpleDevice("itim", Nil) val slaveNode = icacheParams.itimAddr.map { itimAddr => val wordBytes = icacheParams.fetchBytes TLManagerNode(Seq(TLManagerPortParameters( Seq(TLManagerParameters( address = Seq(AddressSet(itimAddr, size-1)), + resources = device.reg, regionType = RegionType.UNCACHED, executable = true, supportsPutFull = TransferSizes(1, wordBytes), diff --git a/src/main/scala/rocket/ScratchpadSlavePort.scala b/src/main/scala/rocket/ScratchpadSlavePort.scala index df9312df..f2681fb2 100644 --- a/src/main/scala/rocket/ScratchpadSlavePort.scala +++ b/src/main/scala/rocket/ScratchpadSlavePort.scala @@ -15,7 +15,7 @@ import util._ class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends LazyModule with HasCoreParameters { - val device = new MemoryDevice + val device = new SimpleDevice("dtim", Nil) val node = TLManagerNode(Seq(TLManagerPortParameters( Seq(TLManagerParameters( address = List(address), diff --git a/src/main/scala/uncore/tilelink2/SRAM.scala b/src/main/scala/uncore/tilelink2/SRAM.scala index e4b3e43b..05cea3b8 100644 --- a/src/main/scala/uncore/tilelink2/SRAM.scala +++ b/src/main/scala/uncore/tilelink2/SRAM.scala @@ -8,10 +8,9 @@ import config._ import diplomacy._ import util._ -class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule +class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4, name: Option[String] = None)(implicit p: Parameters) extends LazyModule { - val device = new MemoryDevice - + val device = name.map(new SimpleDevice(_, Nil)).getOrElse(new MemoryDevice) val node = TLManagerNode(Seq(TLManagerPortParameters( Seq(TLManagerParameters( address = List(address), From 1c97a2a94c6874913f19370d3741cd76e9e4d6d2 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Tue, 20 Jun 2017 16:11:57 -0700 Subject: [PATCH 3/5] allow re-positionable PLIC and Clint, and change coreplex internal network names --- src/main/scala/coreplex/BaseCoreplex.scala | 8 ++- src/main/scala/coreplex/Configs.scala | 3 +- src/main/scala/coreplex/CoreplexNetwork.scala | 50 ++++++++----------- src/main/scala/coreplex/ISPPort.scala | 2 +- src/main/scala/coreplex/RISCVPlatform.scala | 17 ++++--- src/main/scala/coreplex/RocketTiles.scala | 6 +-- src/main/scala/groundtest/Configs.scala | 1 - src/main/scala/groundtest/Coreplex.scala | 4 +- src/main/scala/groundtest/TraceGen.scala | 2 +- .../scala/groundtest/TrafficGenerator.scala | 2 +- src/main/scala/uncore/devices/Clint.scala | 16 +++--- src/main/scala/uncore/devices/Plic.scala | 12 +++-- 12 files changed, 65 insertions(+), 58 deletions(-) diff --git a/src/main/scala/coreplex/BaseCoreplex.scala b/src/main/scala/coreplex/BaseCoreplex.scala index 4d2f0b59..d3062d83 100644 --- a/src/main/scala/coreplex/BaseCoreplex.scala +++ b/src/main/scala/coreplex/BaseCoreplex.scala @@ -46,10 +46,14 @@ case object BootROMFile extends Field[String] trait HasCoreplexParameters { implicit val p: Parameters lazy val tilesParams = p(RocketTilesKey) - lazy val cbusConfig = p(CBusConfig) - lazy val l1tol2Config = p(L1toL2Config) + lazy val sbusConfig = p(L1toL2Config) + lazy val pbusConfig = p(CBusConfig) lazy val nTiles = tilesParams.size lazy val l2Config = p(BankedL2Config) + def sbusBeatBytes = sbusConfig.beatBytes + def sbusBlockBytes = p(CacheBlockBytes) + def pbusBeatBytes = pbusConfig.beatBytes + def pbusBlockBytes = sbusBlockBytes } case class CoreplexParameters(implicit val p: Parameters) extends HasCoreplexParameters diff --git a/src/main/scala/coreplex/Configs.scala b/src/main/scala/coreplex/Configs.scala index 3a3bb958..35dce9e3 100644 --- a/src/main/scala/coreplex/Configs.scala +++ b/src/main/scala/coreplex/Configs.scala @@ -21,11 +21,12 @@ class BaseCoreplexConfig extends Config ((site, here, up) => { case XLen => 64 // Applies to all cores case ResetVectorBits => site(PAddrBits) case MaxHartIdBits => log2Up(site(NTiles)) - case MaxPriorityLevels => 7 case BuildCore => (p: Parameters) => new Rocket()(p) case RocketCrossing => SynchronousCrossing() case RocketTilesKey => Nil case DMKey => DefaultDebugModuleConfig(site(XLen)) + case PLICKey => PLICParams() + case ClintKey => ClintParams() case NTiles => site(RocketTilesKey).size case CBusConfig => TLBusConfig(beatBytes = site(XLen)/8) case L1toL2Config => TLBusConfig(beatBytes = site(XLen)/8) // increase for more PCIe bandwidth diff --git a/src/main/scala/coreplex/CoreplexNetwork.scala b/src/main/scala/coreplex/CoreplexNetwork.scala index 7d64ec8c..70eb30e4 100644 --- a/src/main/scala/coreplex/CoreplexNetwork.scala +++ b/src/main/scala/coreplex/CoreplexNetwork.scala @@ -13,46 +13,40 @@ trait CoreplexNetwork extends HasCoreplexParameters { val module: CoreplexNetworkModule def bindingTree: ResourceMap - val tile_splitter = LazyModule(new TLSplitter) + // TODO: do we need one of these? val cbus = LazyModule(new TLXbar) // Locally-visible peripheral devices + val sbus = LazyModule(new TLXbar) // Globally-visible high-bandwidth devices + val pbus = LazyModule(new TLXbar) // Globally-visible low-bandwidth devices + val tile_splitter = LazyModule(new TLSplitter) // Allows cycle-free connection to external networks + val int_xbar = LazyModule(new IntXbar) // Interrupt crossbar - val l1tol2 = LazyModule(new TLXbar) - val l1tol2_beatBytes = l1tol2Config.beatBytes - val l1tol2_lineBytes = p(CacheBlockBytes) + val mmio = TLOutputNode() // Exernal memory-mapped IO slaves + val mmioInt = IntInputNode() // Exernal devices' interrupts + val l2in = TLInputNode() // External masters talking to the frontside of the shared cache + val l2out = TLOutputNode() // External slaves hanging off the backside of the shared cache - val cbus = LazyModule(new TLXbar) - val cbus_beatBytes = cbusConfig.beatBytes - val cbus_lineBytes = l1tol2_lineBytes - - val intBar = LazyModule(new IntXbar) - - val mmio = TLOutputNode() - val mmioInt = IntInputNode() - val l2in = TLInputNode() - val l2out = TLOutputNode() - - intBar.intnode := mmioInt + int_xbar.intnode := mmioInt // Allows a variable number of inputs from outside to the Xbar private val l2in_buffer = LazyModule(new TLBuffer) private val l2in_fifo = LazyModule(new TLFIFOFixer) - l1tol2.node :=* l2in_fifo.node - l1tol2.node :=* tile_splitter.node + sbus.node :=* l2in_fifo.node + sbus.node :=* tile_splitter.node l2in_fifo.node :=* l2in_buffer.node l2in_buffer.node :=* l2in private val l2out_buffer = LazyModule(new TLBuffer(BufferParams.flow, BufferParams.none)) l2out :*= l2out_buffer.node - l2out_buffer.node :*= l1tol2.node + l2out_buffer.node :*= sbus.node - cbus.node := + pbus.node := TLBuffer()( TLAtomicAutomata(arithmetic = true)( // disable once TLB uses TL2 metadata - TLWidthWidget(l1tol2_beatBytes)( - l1tol2.node))) + TLWidthWidget(sbusBeatBytes)( + sbus.node))) mmio := - TLWidthWidget(l1tol2_beatBytes)( - l1tol2.node) + TLWidthWidget(sbusBeatBytes)( + sbus.node) val root = new Device { def describe(resources: ResourceBindings): Description = { @@ -168,16 +162,16 @@ trait BankedL2CoherenceManagers extends CoreplexNetwork { require (isPow2(l2Config.nMemoryChannels) || l2Config.nMemoryChannels == 0) require (isPow2(l2Config.nBanksPerChannel)) - require (isPow2(l1tol2_lineBytes)) + require (isPow2(sbusBlockBytes)) private val (in, out) = l2Config.coherenceManager(p, this) - private val mask = ~BigInt((l2Config.nBanks-1) * l1tol2_lineBytes) + private val mask = ~BigInt((l2Config.nBanks-1) * sbusBlockBytes) val mem = Seq.tabulate(l2Config.nMemoryChannels) { channel => val node = TLOutputNode() for (bank <- 0 until l2Config.nBanksPerChannel) { val offset = (bank * l2Config.nMemoryChannels) + channel - in := l1tol2.node - node := TLFilter(AddressSet(offset * l1tol2_lineBytes, mask))(out) + in := sbus.node + node := TLFilter(AddressSet(offset * sbusBlockBytes, mask))(out) } node } diff --git a/src/main/scala/coreplex/ISPPort.scala b/src/main/scala/coreplex/ISPPort.scala index 4296cd20..eb60873f 100644 --- a/src/main/scala/coreplex/ISPPort.scala +++ b/src/main/scala/coreplex/ISPPort.scala @@ -27,7 +27,7 @@ trait HasISPPort extends CoreplexNetwork { private val in_async = LazyModule(new TLAsyncCrossingSink) in_async.node :=* isp_in - l1tol2.node :=* in_async.node + sbus.node :=* in_async.node } trait HasISPPortBundle extends CoreplexNetworkBundle { diff --git a/src/main/scala/coreplex/RISCVPlatform.scala b/src/main/scala/coreplex/RISCVPlatform.scala index ec65c192..e52af304 100644 --- a/src/main/scala/coreplex/RISCVPlatform.scala +++ b/src/main/scala/coreplex/RISCVPlatform.scala @@ -10,20 +10,23 @@ import uncore.tilelink2._ import uncore.devices._ import util._ -case object MaxPriorityLevels extends Field[Int] +/** Number of tiles */ +case object NTiles extends Field[Int] +case object PLICKey extends Field[PLICParams] +case object ClintKey extends Field[ClintParams] trait CoreplexRISCVPlatform extends CoreplexNetwork { val module: CoreplexRISCVPlatformModule val debug = LazyModule(new TLDebugModule()) - val plic = LazyModule(new TLPLIC(maxPriorities = p(MaxPriorityLevels))) - val clint = LazyModule(new CoreplexLocalInterrupter) + debug.node := TLFragmenter(pbusBeatBytes, pbusBlockBytes)(pbus.node) - debug.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node) - plic.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node) - clint.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node) + val plic = LazyModule(new TLPLIC(p(PLICKey))) + plic.node := TLFragmenter(pbusBeatBytes, pbusBlockBytes)(pbus.node) + plic.intnode := int_xbar.intnode - plic.intnode := intBar.intnode + val clint = LazyModule(new CoreplexLocalInterrupter(nTiles, p(ClintKey))) + clint.node := TLFragmenter(pbusBeatBytes, pbusBlockBytes)(pbus.node) lazy val dts = DTS(bindingTree) lazy val dtb = DTB(dts) diff --git a/src/main/scala/coreplex/RocketTiles.scala b/src/main/scala/coreplex/RocketTiles.scala index 2e8e9562..4b619017 100644 --- a/src/main/scala/coreplex/RocketTiles.scala +++ b/src/main/scala/coreplex/RocketTiles.scala @@ -65,7 +65,7 @@ trait HasRocketTiles extends CoreplexRISCVPlatform { buffer.node :=* wrapper.masterNode fixer.node :=* buffer.node tile_splitter.node :=* fixer.node - wrapper.slaveNode :*= cbus.node + wrapper.slaveNode :*= pbus.node wrapper.asyncIntNode := asyncIntXbar.intnode wrapper.periphIntNode := periphIntXbar.intnode wrapper.coreIntNode := coreIntXbar.intnode @@ -87,7 +87,7 @@ trait HasRocketTiles extends CoreplexRISCVPlatform { wrapper.asyncIntNode := asyncIntXbar.intnode wrapper.periphIntNode := periphIntXbar.intnode wrapper.coreIntNode := coreIntXbar.intnode - source.node :*= cbus.node + source.node :*= pbus.node (io: HasRocketTilesBundle) => { wrapper.module.clock := io.tcrs(i).clock wrapper.module.reset := io.tcrs(i).reset @@ -107,7 +107,7 @@ trait HasRocketTiles extends CoreplexRISCVPlatform { wrapper.asyncIntNode := asyncIntXbar.intnode wrapper.periphIntNode := periphIntXbar.intnode wrapper.coreIntNode := coreIntXbar.intnode - source.node :*= cbus.node + source.node :*= pbus.node (io: HasRocketTilesBundle) => { wrapper.module.clock := io.tcrs(i).clock wrapper.module.reset := io.tcrs(i).reset diff --git a/src/main/scala/groundtest/Configs.scala b/src/main/scala/groundtest/Configs.scala index 63ba2737..05ad31e1 100644 --- a/src/main/scala/groundtest/Configs.scala +++ b/src/main/scala/groundtest/Configs.scala @@ -10,7 +10,6 @@ import uncore.tilelink._ import uncore.coherence._ import uncore.agents._ import uncore.util._ -import uncore.devices.NTiles import tile.TileKey import junctions._ import config._ diff --git a/src/main/scala/groundtest/Coreplex.scala b/src/main/scala/groundtest/Coreplex.scala index e4b133d0..aa2ec4e9 100644 --- a/src/main/scala/groundtest/Coreplex.scala +++ b/src/main/scala/groundtest/Coreplex.scala @@ -44,8 +44,8 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex { tile_splitter.node :=* fixer.node tiles.foreach { fixer.node :=* _.masterNode } - val cbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, cbus_beatBytes)) - cbusRAM.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node) + val pbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, pbusBlockBytes)) + pbusRAM.node := TLFragmenter(pbusBeatBytes, pbusBlockBytes)(pbus.node) override lazy val module = new GroundTestCoreplexModule(this, () => new GroundTestCoreplexBundle(this)) } diff --git a/src/main/scala/groundtest/TraceGen.scala b/src/main/scala/groundtest/TraceGen.scala index 37880862..d2e233bc 100644 --- a/src/main/scala/groundtest/TraceGen.scala +++ b/src/main/scala/groundtest/TraceGen.scala @@ -22,7 +22,7 @@ package groundtest import Chisel._ import uncore.tilelink._ import uncore.constants._ -import uncore.devices.NTiles +import coreplex.NTiles import rocket._ import tile._ import util.{Timer, DynamicTimer} diff --git a/src/main/scala/groundtest/TrafficGenerator.scala b/src/main/scala/groundtest/TrafficGenerator.scala index 2d1c77f1..0eefcd29 100644 --- a/src/main/scala/groundtest/TrafficGenerator.scala +++ b/src/main/scala/groundtest/TrafficGenerator.scala @@ -5,7 +5,7 @@ package groundtest import Chisel._ import uncore.tilelink._ -import uncore.devices.NTiles +import coreplex.NTiles import uncore.constants._ import junctions._ import rocket._ diff --git a/src/main/scala/uncore/devices/Clint.scala b/src/main/scala/uncore/devices/Clint.scala index 673106d8..5a7d3c4e 100644 --- a/src/main/scala/uncore/devices/Clint.scala +++ b/src/main/scala/uncore/devices/Clint.scala @@ -14,9 +14,6 @@ import scala.math.{min,max} import config._ import tile.XLen -/** Number of tiles */ -case object NTiles extends Field[Int] - object ClintConsts { def msipOffset(hart: Int) = hart * msipBytes @@ -30,7 +27,12 @@ object ClintConsts def ints = 2 } -class CoreplexLocalInterrupter(address: BigInt = 0x02000000)(implicit p: Parameters) extends LazyModule +case class ClintParams(baseAddress: BigInt = 0x02000000) +{ + def address = AddressSet(baseAddress, ClintConsts.size-1) +} + +class CoreplexLocalInterrupter(nTiles: Int, params: ClintParams)(implicit p: Parameters) extends LazyModule { import ClintConsts._ @@ -40,7 +42,7 @@ class CoreplexLocalInterrupter(address: BigInt = 0x02000000)(implicit p: Paramet } val node = TLRegisterNode( - address = Seq(AddressSet(address, size-1)), + address = Seq(params.address), device = device, beatBytes = p(XLen)/8) @@ -64,8 +66,8 @@ class CoreplexLocalInterrupter(address: BigInt = 0x02000000)(implicit p: Paramet reg := newTime >> i } - val timecmp = Seq.fill(p(NTiles)) { Seq.fill(timeWidth/regWidth)(Reg(UInt(width = regWidth))) } - val ipi = Seq.fill(p(NTiles)) { RegInit(UInt(0, width = 1)) } + val timecmp = Seq.fill(nTiles) { Seq.fill(timeWidth/regWidth)(Reg(UInt(width = regWidth))) } + val ipi = Seq.fill(nTiles) { RegInit(UInt(0, width = 1)) } io.int.zipWithIndex.foreach { case (int, i) => int(0) := ipi(i)(0) // msip diff --git a/src/main/scala/uncore/devices/Plic.scala b/src/main/scala/uncore/devices/Plic.scala index 0c0e26aa..a71b7d5c 100644 --- a/src/main/scala/uncore/devices/Plic.scala +++ b/src/main/scala/uncore/devices/Plic.scala @@ -53,11 +53,15 @@ object PLICConsts require(hartBase >= enableBase(maxHarts)) } -/** Platform-Level Interrupt Controller */ -class TLPLIC(maxPriorities: Int, address: BigInt = 0xC000000)(implicit p: Parameters) extends LazyModule +case class PLICParams(baseAddress: BigInt = 0xC000000, maxPriorities: Int = 7) { require (maxPriorities >= 0) + def address = AddressSet(baseAddress, PLICConsts.size-1) +} +/** Platform-Level Interrupt Controller */ +class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule +{ // plic0 => max devices 1023 val device = new SimpleDevice("interrupt-controller", Seq("riscv,plic0")) { override val alwaysExtended = true @@ -73,7 +77,7 @@ class TLPLIC(maxPriorities: Int, address: BigInt = 0xC000000)(implicit p: Parame } val node = TLRegisterNode( - address = Seq(AddressSet(address, PLICConsts.size-1)), + address = Seq(params.address), device = device, beatBytes = p(XLen)/8, undefZero = false, @@ -87,7 +91,7 @@ class TLPLIC(maxPriorities: Int, address: BigInt = 0xC000000)(implicit p: Parame /* Negotiated sizes */ def nDevices: Int = intnode.edgesIn.map(_.source.num).sum - def nPriorities = min(maxPriorities, nDevices) + def nPriorities = min(params.maxPriorities, nDevices) def nHarts = intnode.edgesOut.map(_.source.num).sum // Assign all the devices unique ranges From 2f2fe0a9736e675ac57c0ee2c55c54ca9efcb38b Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Tue, 20 Jun 2017 17:21:53 -0700 Subject: [PATCH 4/5] clint: don't ask for what you know (nTiles) --- src/main/scala/coreplex/RISCVPlatform.scala | 2 +- src/main/scala/uncore/devices/Clint.scala | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/main/scala/coreplex/RISCVPlatform.scala b/src/main/scala/coreplex/RISCVPlatform.scala index e52af304..b42ed557 100644 --- a/src/main/scala/coreplex/RISCVPlatform.scala +++ b/src/main/scala/coreplex/RISCVPlatform.scala @@ -25,7 +25,7 @@ trait CoreplexRISCVPlatform extends CoreplexNetwork { plic.node := TLFragmenter(pbusBeatBytes, pbusBlockBytes)(pbus.node) plic.intnode := int_xbar.intnode - val clint = LazyModule(new CoreplexLocalInterrupter(nTiles, p(ClintKey))) + val clint = LazyModule(new CoreplexLocalInterrupter(p(ClintKey))) clint.node := TLFragmenter(pbusBeatBytes, pbusBlockBytes)(pbus.node) lazy val dts = DTS(bindingTree) diff --git a/src/main/scala/uncore/devices/Clint.scala b/src/main/scala/uncore/devices/Clint.scala index 5a7d3c4e..90e8aa13 100644 --- a/src/main/scala/uncore/devices/Clint.scala +++ b/src/main/scala/uncore/devices/Clint.scala @@ -32,7 +32,7 @@ case class ClintParams(baseAddress: BigInt = 0x02000000) def address = AddressSet(baseAddress, ClintConsts.size-1) } -class CoreplexLocalInterrupter(nTiles: Int, params: ClintParams)(implicit p: Parameters) extends LazyModule +class CoreplexLocalInterrupter(params: ClintParams)(implicit p: Parameters) extends LazyModule { import ClintConsts._ @@ -66,6 +66,7 @@ class CoreplexLocalInterrupter(nTiles: Int, params: ClintParams)(implicit p: Par reg := newTime >> i } + val nTiles = intnode.edgesOut.size val timecmp = Seq.fill(nTiles) { Seq.fill(timeWidth/regWidth)(Reg(UInt(width = regWidth))) } val ipi = Seq.fill(nTiles) { RegInit(UInt(0, width = 1)) } From bf431c0a53fb7eb61c7f2fe47c5004f8a49f136c Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Tue, 20 Jun 2017 18:05:08 -0700 Subject: [PATCH 5/5] groundtest: fix test ram width --- src/main/scala/groundtest/Coreplex.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/groundtest/Coreplex.scala b/src/main/scala/groundtest/Coreplex.scala index aa2ec4e9..bfd6d887 100644 --- a/src/main/scala/groundtest/Coreplex.scala +++ b/src/main/scala/groundtest/Coreplex.scala @@ -44,7 +44,7 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex { tile_splitter.node :=* fixer.node tiles.foreach { fixer.node :=* _.masterNode } - val pbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, pbusBlockBytes)) + val pbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, pbusBeatBytes)) pbusRAM.node := TLFragmenter(pbusBeatBytes, pbusBlockBytes)(pbus.node) override lazy val module = new GroundTestCoreplexModule(this, () => new GroundTestCoreplexBundle(this))