From 0fcacd37df0d404ede8452b103bbd9ec71cf0ff2 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Fri, 9 Mar 2018 15:10:43 -0800
Subject: [PATCH] RegFieldDesc: mark some more registers as volatile

---
 src/main/scala/devices/tilelink/CLINT.scala | 10 ++++++----
 src/main/scala/tilelink/Example.scala       |  2 +-
 2 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/src/main/scala/devices/tilelink/CLINT.scala b/src/main/scala/devices/tilelink/CLINT.scala
index 5c9d3358..cb1f340b 100644
--- a/src/main/scala/devices/tilelink/CLINT.scala
+++ b/src/main/scala/devices/tilelink/CLINT.scala
@@ -82,10 +82,12 @@ class CLINT(params: CLINTParams, beatBytes: Int)(implicit p: Parameters) extends
      */
 
     node.regmap(
-      0                -> RegFieldGroup ("msip", Some("MSIP Bits"), ipi.zipWithIndex.map{ case (r, i) => RegField(ipiWidth, r, RegFieldDesc(s"msip_$i", s"MSIP bit for Hart $i", reset=Some(0)))}),
-      timecmpOffset(0) -> timecmp.zipWithIndex.flatMap{ case (t, i) =>
-        RegFieldGroup(s"mtimecmp_$i", Some(s"MTIMECMP for hart $i"), RegField.bytes(t, Some(RegFieldDesc(s"mtimecmp_$i", "", reset=None))))},
-      timeOffset       -> RegFieldGroup("mtime", Some("Timer Register"), RegField.bytes(time, Some(RegFieldDesc("mtime", "", reset=Some(0)))))
+      0                -> RegFieldGroup ("msip", Some("MSIP Bits"), ipi.zipWithIndex.map{ case (r, i) =>
+        RegField(ipiWidth, r, RegFieldDesc(s"msip_$i", s"MSIP bit for Hart $i", reset=Some(0)))}),
+      timecmpOffset(0) -> timecmp.zipWithIndex.flatMap{ case (t, i) => RegFieldGroup(s"mtimecmp_$i", Some(s"MTIMECMP for hart $i"),
+          RegField.bytes(t, Some(RegFieldDesc(s"mtimecmp_$i", "", reset=None))))},
+      timeOffset       -> RegFieldGroup("mtime", Some("Timer Register"),
+        RegField.bytes(time, Some(RegFieldDesc("mtime", "", reset=Some(0), volatile=true))))
     )
   }
 }
diff --git a/src/main/scala/tilelink/Example.scala b/src/main/scala/tilelink/Example.scala
index e5f3104c..bfd85b14 100644
--- a/src/main/scala/tilelink/Example.scala
+++ b/src/main/scala/tilelink/Example.scala
@@ -35,7 +35,7 @@ trait ExampleModule extends HasRegMap
         Some(RegFieldDesc("pending", "Pending: Example of a special (W1ToC) Register. " +
           "Writing a bit here causes it to be reset to 0. " +
           "The bits are set when the corresponding bit in 'state' is high.",
-          reset=Some(0xF)))))
+          reset=Some(0xF), volatile=true))))
   )
 }