From 0ee1ce4366efe83e100fd681c2ad95c650945c4f Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Wed, 10 Aug 2016 09:49:56 -0700 Subject: [PATCH] separate Coreplex and TopLevel parameter traits --- src/main/scala/Coreplex.scala | 46 +++++++++++++++++++-------- src/main/scala/DirectGroundTest.scala | 15 ++++----- src/main/scala/RocketChip.scala | 11 ------- 3 files changed, 38 insertions(+), 34 deletions(-) diff --git a/src/main/scala/Coreplex.scala b/src/main/scala/Coreplex.scala index 806f959d..d236adcc 100644 --- a/src/main/scala/Coreplex.scala +++ b/src/main/scala/Coreplex.scala @@ -41,12 +41,27 @@ case object ExportBusPort extends Field[Boolean] /** Function for building Coreplex */ case object BuildCoreplex extends Field[Parameters => Coreplex] +trait HasCoreplexParameters { + implicit val p: Parameters + lazy val nTiles = p(NTiles) + lazy val nCachedTilePorts = p(NCachedTileLinkPorts) + lazy val nUncachedTilePorts = p(NUncachedTileLinkPorts) + lazy val nMemChannels = p(NMemoryChannels) + lazy val nBanksPerMemChannel = p(NBanksPerMemoryChannel) + lazy val nBanks = nMemChannels*nBanksPerMemChannel + lazy val lsb = p(BankIdLSB) + lazy val outermostParams = p.alterPartial({ case TLId => "Outermost" }) + lazy val outermostMMIOParams = p.alterPartial({ case TLId => "MMIO_Outermost" }) + lazy val exportBus = p(ExportBusPort) + lazy val exportMMIO = p(ExportMMIOPort) +} + /** Wrapper around everything that isn't a Tile. * * Usually this is clocked and/or place-and-routed separately from the Tiles. */ class Uncore(implicit val p: Parameters) extends Module - with HasTopLevelParameters { + with HasCoreplexParameters { val io = new Bundle { val mem = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outermostParams)) @@ -60,7 +75,7 @@ class Uncore(implicit val p: Parameters) extends Module } val outmemsys = if (nCachedTilePorts + nUncachedTilePorts > 0) - Module(new OuterMemorySystem) // NoC, LLC and SerDes + Module(new DefaultOuterMemorySystem) // NoC, LLC and SerDes else Module(new DummyOuterMemorySystem) outmemsys.io.incoherent foreach (_ := false) outmemsys.io.tiles_uncached <> io.tiles_uncached @@ -126,8 +141,8 @@ class Uncore(implicit val p: Parameters) extends Module } } -abstract class AbstractOuterMemorySystem(implicit val p: Parameters) - extends Module with HasTopLevelParameters { +abstract class OuterMemorySystem(implicit val p: Parameters) + extends Module with HasCoreplexParameters { val io = new Bundle { val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip @@ -139,7 +154,7 @@ abstract class AbstractOuterMemorySystem(implicit val p: Parameters) } /** Use in place of OuterMemorySystem if there are no clients to connect. */ -class DummyOuterMemorySystem(implicit p: Parameters) extends AbstractOuterMemorySystem()(p) { +class DummyOuterMemorySystem(implicit p: Parameters) extends OuterMemorySystem()(p) { require(nCachedTilePorts + nUncachedTilePorts == 0) require(io.bus.isEmpty) @@ -155,7 +170,7 @@ class DummyOuterMemorySystem(implicit p: Parameters) extends AbstractOuterMemory /** The whole outer memory hierarchy, including a NoC, some kind of coherence * manager agent, and a converter from TileLink to MemIO. */ -class OuterMemorySystem(implicit p: Parameters) extends AbstractOuterMemorySystem()(p) { +class DefaultOuterMemorySystem(implicit p: Parameters) extends OuterMemorySystem()(p) { // Create a simple L1toL2 NoC between the tiles and the banks of outer memory // Cached ports are first in client list, making sharerToClientId just an indentity function // addrToBank is sed to hash physical addresses (of cache blocks) to banks (and thereby memory channels) @@ -212,15 +227,18 @@ class OuterMemorySystem(implicit p: Parameters) extends AbstractOuterMemorySyste io.mem <> mem_ic.io.out } +class CoreplexIO(implicit val p: Parameters) extends ParameterizedBundle()(p) + with HasCoreplexParameters { + val mem = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outermostParams)) + val bus = if (p(ExportBusPort)) Some(new ClientUncachedTileLinkIO().flip) else None + val mmio = if(p(ExportMMIOPort)) Some(new ClientUncachedTileLinkIO()(outermostMMIOParams)) else None + val interrupts = Vec(p(NExtInterrupts), Bool()).asInput + val debug = new DebugBusIO()(p).flip +} + abstract class Coreplex(implicit val p: Parameters) extends Module - with HasTopLevelParameters { - val io = new Bundle { - val mem = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outermostParams)) - val bus = if (p(ExportBusPort)) Some(new ClientUncachedTileLinkIO().flip) else None - val mmio = if(p(ExportMMIOPort)) Some(new ClientUncachedTileLinkIO()(outermostMMIOParams)) else None - val interrupts = Vec(p(NExtInterrupts), Bool()).asInput - val debug = new DebugBusIO()(p).flip - } + with HasCoreplexParameters { + val io = new CoreplexIO } class DefaultCoreplex(topParams: Parameters) extends Coreplex()(topParams) { diff --git a/src/main/scala/DirectGroundTest.scala b/src/main/scala/DirectGroundTest.scala index c0ba9df1..d5156ab5 100644 --- a/src/main/scala/DirectGroundTest.scala +++ b/src/main/scala/DirectGroundTest.scala @@ -8,10 +8,8 @@ import uncore.agents._ case object ExportGroundTestStatus extends Field[Boolean] -class DirectGroundTestTop(topParams: Parameters) extends Module - with HasTopLevelParameters { - implicit val p = topParams - val io = new TopIO { +class DirectGroundTestCoreplex(topParams: Parameters) extends Coreplex()(topParams) { + override val io = new CoreplexIO { // Need to export this for FPGA testing, but not for simulator val status = if (p(ExportGroundTestStatus)) Some(new GroundTestStatus) else None } @@ -20,8 +18,8 @@ class DirectGroundTestTop(topParams: Parameters) extends Module io.debug.req.ready := Bool(false) io.debug.resp.valid := Bool(false) - require(io.mmio_axi.isEmpty && io.mmio_ahb.isEmpty && io.mmio_tl.isEmpty) - require(io.mem_ahb.isEmpty && io.mem_tl.isEmpty) + require(!exportMMIO) + require(!exportBus) require(nMemChannels == 1) require(nTiles == 1) @@ -39,9 +37,8 @@ class DirectGroundTestTop(topParams: Parameters) extends Module nBanksPerMemChannel, nMemChannels)(outermostParams)) mem_ic.io.in <> test.io.mem - io.mem_axi.zip(mem_ic.io.out).foreach { case (nasti, tl) => - TopUtils.connectTilelinkNasti(nasti, tl)(outermostParams) - } + io.mem <> mem_ic.io.out + io.status.map { status => val s_running :: s_finished :: s_errored :: s_timeout :: Nil = Enum(Bits(), 4) val state = Reg(init = s_running) diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 721fab91..1459b043 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -44,22 +44,11 @@ case object ExtMMIOPorts extends Field[Seq[AddrMapEntry]] /** Utility trait for quick access to some relevant parameters */ trait HasTopLevelParameters { implicit val p: Parameters - lazy val nTiles = p(NTiles) - lazy val nCachedTilePorts = p(NCachedTileLinkPorts) - lazy val nUncachedTilePorts = p(NUncachedTileLinkPorts) - lazy val csrAddrBits = 12 lazy val tMemChannels = p(TMemoryChannels) lazy val nMemChannels = p(NMemoryChannels) lazy val nMemAXIChannels = if (tMemChannels == BusType.AXI) nMemChannels else 0 lazy val nMemAHBChannels = if (tMemChannels == BusType.AHB) nMemChannels else 0 lazy val nMemTLChannels = if (tMemChannels == BusType.TL) nMemChannels else 0 - lazy val nBanksPerMemChannel = p(NBanksPerMemoryChannel) - lazy val nBanks = nMemChannels*nBanksPerMemChannel - lazy val lsb = p(BankIdLSB) - lazy val nMemReqs = p(NOutstandingMemReqsPerChannel) - lazy val mifAddrBits = p(MIFAddrBits) - lazy val mifDataBeats = p(MIFDataBeats) - lazy val xLen = p(XLen) lazy val outermostParams = p.alterPartial({ case TLId => "Outermost" }) lazy val outermostMMIOParams = p.alterPartial({ case TLId => "MMIO_Outermost" }) lazy val exportBus = p(ExportBusPort)