declaring success on FPU for now
This commit is contained in:
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297223a13c
commit
0ec7767c13
@ -546,7 +546,7 @@ class rocketCtrl extends Component
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var id_stall_fpu = Bool(false)
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if (HAVE_FPU) {
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val fp_sboard = new rocketCtrlSboard(32, 4, 2);
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val fp_sboard = new rocketCtrlSboard(32, 4, 3);
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fp_sboard.io.r(0).addr := id_raddr1.toUFix
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fp_sboard.io.r(1).addr := id_raddr2.toUFix
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fp_sboard.io.r(2).addr := id_raddr3.toUFix
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@ -560,6 +560,10 @@ class rocketCtrl extends Component
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fp_sboard.io.w(1).data := Bool(false)
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fp_sboard.io.w(1).addr := io.dpath.fp_sboard_clra
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fp_sboard.io.w(2).en := io.fpu.sboard_clr
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fp_sboard.io.w(2).data := Bool(false)
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fp_sboard.io.w(2).addr := io.fpu.sboard_clra
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id_stall_fpu = io.fpu.dec.ren1 && fp_sboard.io.r(0).data ||
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io.fpu.dec.ren2 && fp_sboard.io.r(1).data ||
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io.fpu.dec.ren3 && fp_sboard.io.r(2).data ||
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@ -120,10 +120,21 @@ class rocketFPUDecoder extends Component
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FMIN_S -> List(Y,FCMD_MIN, Y,N,Y,Y,N,Y,N,N,Y,N,N,N,N),
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FMAX_S -> List(Y,FCMD_MAX, Y,N,Y,Y,N,Y,N,N,Y,N,N,N,N),
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FMIN_D -> List(Y,FCMD_MIN, Y,N,Y,Y,N,N,N,N,Y,N,N,N,N),
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FMAX_D -> List(Y,FCMD_MAX, Y,N,Y,Y,N,N,N,N,Y,N,N,N,N)
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// FADD_S -> List(Y,FCMD_ADD, Y,Y,Y,Y,N,Y,N,N,N,Y,N,N,N),
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// FSUB_S -> List(Y,FCMD_SUB, Y,Y,Y,Y,N,Y,N,N,N,Y,N,N,N),
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// FMUL_S -> List(Y,FCMD_MUL, Y,Y,Y,Y,N,Y,N,N,N,Y,N,N,N),
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FMAX_D -> List(Y,FCMD_MAX, Y,N,Y,Y,N,N,N,N,Y,N,N,N,N),
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FADD_S -> List(Y,FCMD_ADD, Y,Y,Y,Y,N,Y,N,N,N,Y,N,N,N),
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FSUB_S -> List(Y,FCMD_SUB, Y,Y,Y,Y,N,Y,N,N,N,Y,N,N,N),
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FMUL_S -> List(Y,FCMD_MUL, Y,Y,Y,Y,N,Y,N,N,N,Y,N,N,N),
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FADD_D -> List(Y,FCMD_ADD, Y,Y,Y,Y,N,N,N,N,N,Y,N,N,N),
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FSUB_D -> List(Y,FCMD_SUB, Y,Y,Y,Y,N,N,N,N,N,Y,N,N,N),
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FMUL_D -> List(Y,FCMD_MUL, Y,Y,Y,Y,N,N,N,N,N,Y,N,N,N),
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FMADD_S -> List(Y,FCMD_MADD, Y,Y,Y,Y,Y,Y,N,N,N,Y,N,N,N),
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FMSUB_S -> List(Y,FCMD_MSUB, Y,Y,Y,Y,Y,Y,N,N,N,Y,N,N,N),
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FNMADD_S -> List(Y,FCMD_NMADD, Y,Y,Y,Y,Y,Y,N,N,N,Y,N,N,N),
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FNMSUB_S -> List(Y,FCMD_NMSUB, Y,Y,Y,Y,Y,Y,N,N,N,Y,N,N,N),
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FMADD_D -> List(Y,FCMD_MADD, Y,Y,Y,Y,Y,N,N,N,N,Y,N,N,N),
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FMSUB_D -> List(Y,FCMD_MSUB, Y,Y,Y,Y,Y,N,N,N,N,Y,N,N,N),
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FNMADD_D -> List(Y,FCMD_NMADD, Y,Y,Y,Y,Y,N,N,N,N,Y,N,N,N),
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FNMSUB_D -> List(Y,FCMD_NMSUB, Y,Y,Y,Y,Y,N,N,N,N,Y,N,N,N)
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))
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val valid :: cmd :: wen :: sboard :: ren1 :: ren2 :: ren3 :: single :: fromint :: toint :: fastpipe :: fma :: store :: rdfsr :: wrfsr :: Nil = decoder
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@ -164,6 +175,8 @@ class ioCtrlFPU extends Bundle {
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val killx = Bool(OUTPUT)
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val killm = Bool(OUTPUT)
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val dec = new rocketFPUCtrlSigs().asInput
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val sboard_clr = Bool(INPUT)
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val sboard_clra = UFix(5, INPUT)
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}
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class rocketFPIntUnit extends Component
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@ -192,8 +205,8 @@ class rocketFPIntUnit extends Component
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val scmp = new hardfloat.recodedFloat32Compare
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scmp.io.a := io.in1
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scmp.io.b := io.in2
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val scmp_out = (io.cmd(1,0) & Cat(scmp.io.a_lt_b, scmp.io.a_eq_b)).orR
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val scmp_exc = (io.cmd(1,0) & Cat(scmp.io.a_lt_b_invalid, scmp.io.a_eq_b_invalid)).orR << UFix(4)
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val scmp_out = (io.cmd & Cat(scmp.io.a_lt_b, scmp.io.a_eq_b)).orR
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val scmp_exc = (io.cmd & Cat(scmp.io.a_lt_b_invalid, scmp.io.a_eq_b_invalid)).orR << UFix(4)
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val s2i = new hardfloat.recodedFloat32ToAny
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s2i.io.in := io.in1
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@ -203,8 +216,8 @@ class rocketFPIntUnit extends Component
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val dcmp = new hardfloat.recodedFloat64Compare
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dcmp.io.a := io.in1
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dcmp.io.b := io.in2
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val dcmp_out = (io.cmd(1,0) & Cat(dcmp.io.a_lt_b, dcmp.io.a_eq_b)).orR
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val dcmp_exc = (io.cmd(1,0) & Cat(dcmp.io.a_lt_b_invalid, dcmp.io.a_eq_b_invalid)).orR << UFix(4)
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val dcmp_out = (io.cmd & Cat(dcmp.io.a_lt_b, dcmp.io.a_eq_b)).orR
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val dcmp_exc = (io.cmd & Cat(dcmp.io.a_lt_b_invalid, dcmp.io.a_eq_b_invalid)).orR << UFix(4)
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val d2i = new hardfloat.recodedFloat64ToAny
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d2i.io.in := io.in1
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@ -258,7 +271,7 @@ class rocketFPUFastPipe extends Component
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val in2 = Bits(65, INPUT)
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val lt_s = Bool(INPUT)
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val lt_d = Bool(INPUT)
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val out_s = Bits(65, OUTPUT)
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val out_s = Bits(33, OUTPUT)
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val exc_s = Bits(5, OUTPUT)
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val out_d = Bits(65, OUTPUT)
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val exc_d = Bits(5, OUTPUT)
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@ -346,12 +359,96 @@ class rocketFPUFastPipe extends Component
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exc_d := Reg(i2d.io.exceptionFlags)
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}
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io.out_s := Cat(Fill(32,UFix(1)), out_s)
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io.out_s := out_s
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io.exc_s := exc_s
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io.out_d := out_d
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io.exc_d := exc_d
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}
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class rocketFPUSFMAPipe(latency: Int) extends Component
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{
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val io = new Bundle {
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val valid = Bool(INPUT)
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val cmd = Bits(FCMD_WIDTH, INPUT)
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val rm = Bits(3, INPUT)
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val in1 = Bits(33, INPUT)
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val in2 = Bits(33, INPUT)
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val in3 = Bits(33, INPUT)
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val out = Bits(33, OUTPUT)
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val exc = Bits(5, OUTPUT)
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}
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val cmd = Reg() { Bits() }
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val rm = Reg() { Bits() }
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val in1 = Reg() { Bits() }
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val in2 = Reg() { Bits() }
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val in3 = Reg() { Bits() }
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val cmd_fma = io.cmd === FCMD_MADD || io.cmd === FCMD_MSUB ||
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io.cmd === FCMD_NMADD || io.cmd === FCMD_NMSUB
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val cmd_addsub = io.cmd === FCMD_ADD || io.cmd === FCMD_SUB
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when (io.valid) {
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cmd := Cat(io.cmd(1) & (cmd_fma || cmd_addsub), io.cmd(0))
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rm := io.rm
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in1 := io.in1
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in2 := Mux(cmd_addsub, Bits("h80000000"), io.in2)
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in3 := Mux(cmd_fma, io.in3, Mux(cmd_addsub, io.in2, Bits(0)))
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}
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val fma = new hardfloat.mulAddSubRecodedFloat32_1
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fma.io.op := cmd
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fma.io.roundingMode := rm
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fma.io.a := in1
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fma.io.b := in2
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fma.io.c := in3
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io.out := ShiftRegister(latency-1, fma.io.out)
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io.exc := ShiftRegister(latency-1, fma.io.exceptionFlags)
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}
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class rocketFPUDFMAPipe(latency: Int) extends Component
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{
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val io = new Bundle {
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val valid = Bool(INPUT)
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val cmd = Bits(FCMD_WIDTH, INPUT)
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val rm = Bits(3, INPUT)
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val in1 = Bits(65, INPUT)
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val in2 = Bits(65, INPUT)
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val in3 = Bits(65, INPUT)
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val out = Bits(65, OUTPUT)
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val exc = Bits(5, OUTPUT)
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}
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val cmd = Reg() { Bits() }
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val rm = Reg() { Bits() }
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val in1 = Reg() { Bits() }
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val in2 = Reg() { Bits() }
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val in3 = Reg() { Bits() }
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val cmd_fma = io.cmd === FCMD_MADD || io.cmd === FCMD_MSUB ||
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io.cmd === FCMD_NMADD || io.cmd === FCMD_NMSUB
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val cmd_addsub = io.cmd === FCMD_ADD || io.cmd === FCMD_SUB
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when (io.valid) {
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cmd := Cat(io.cmd(1) & (cmd_fma || cmd_addsub), io.cmd(0))
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rm := io.rm
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in1 := io.in1
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in2 := Mux(cmd_addsub, Bits("h8000000000000000"), io.in2)
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in3 := Mux(cmd_fma, io.in3, Mux(cmd_addsub, io.in2, Bits(0)))
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}
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val fma = new hardfloat.mulAddSubRecodedFloat64_1
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fma.io.op := cmd
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fma.io.roundingMode := rm
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fma.io.a := in1
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fma.io.b := in2
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fma.io.c := in3
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io.out := ShiftRegister(latency-1, fma.io.out)
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io.exc := ShiftRegister(latency-1, fma.io.exceptionFlags)
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}
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class rocketFPU(sfma_latency: Int, dfma_latency: Int) extends Component
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{
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val io = new Bundle {
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@ -388,7 +485,8 @@ class rocketFPU(sfma_latency: Int, dfma_latency: Int) extends Component
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val rec_d = new hardfloat.float64ToRecodedFloat64
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rec_s.io.in := load_wb_data
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rec_d.io.in := load_wb_data
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val load_wb_data_recoded = Mux(load_wb_single, Cat(Fill(32,UFix(1)), rec_s.io.out), rec_d.io.out)
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val sp_msbs = Fill(32, UFix(1,1))
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val load_wb_data_recoded = Mux(load_wb_single, Cat(sp_msbs, rec_s.io.out), rec_d.io.out)
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val fsr_rm = Reg() { Bits(width = 3) }
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val fsr_exc = Reg() { Bits(width = 5) }
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@ -403,7 +501,6 @@ class rocketFPU(sfma_latency: Int, dfma_latency: Int) extends Component
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val ex_rs3 = regfile.read(reg_inst(16,12))
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val ex_rm = Mux(reg_inst(11,9) === Bits(7), fsr_rm, reg_inst(11,9))
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val mem_fromint_val = Reg(resetVal = Bool(false))
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val mem_fromint_data = Reg() { Bits() }
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val mem_toint_val = Reg(resetVal = Bool(false))
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val mem_rs1 = Reg() { Bits() }
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@ -412,13 +509,11 @@ class rocketFPU(sfma_latency: Int, dfma_latency: Int) extends Component
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val mem_rm = Reg() { Bits() }
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val mem_wrfsr_val = Reg(resetVal = Bool(false))
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mem_fromint_val := Bool(false)
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mem_toint_val := Bool(false)
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mem_wrfsr_val := Bool(false)
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when (reg_valid) {
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mem_rm := ex_rm
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when (ctrl.fromint || ctrl.wrfsr) {
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mem_fromint_val := !io.ctrl.killx
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mem_fromint_data := io.dpath.fromint_data
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}
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when (ctrl.wrfsr) {
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@ -453,6 +548,7 @@ class rocketFPU(sfma_latency: Int, dfma_latency: Int) extends Component
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io.dpath.store_data := fpiu.io.store_data
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io.dpath.toint_data := fpiu.io.toint_data
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// 2-cycle pipe for int->FP and non-FMA FP->FP ops
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val fastpipe = new rocketFPUFastPipe
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fastpipe.io.single := mem_ctrl.single
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fastpipe.io.cmd := mem_ctrl.cmd
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@ -463,12 +559,31 @@ class rocketFPU(sfma_latency: Int, dfma_latency: Int) extends Component
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fastpipe.io.lt_s := fpiu.io.lt_s
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fastpipe.io.lt_d := fpiu.io.lt_d
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val cmd_fma = mem_ctrl.cmd === FCMD_MADD || mem_ctrl.cmd === FCMD_MSUB ||
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mem_ctrl.cmd === FCMD_NMADD || mem_ctrl.cmd === FCMD_NMSUB
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val cmd_addsub = mem_ctrl.cmd === FCMD_ADD || mem_ctrl.cmd === FCMD_SUB
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val sfma = new rocketFPUSFMAPipe(sfma_latency-1)
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sfma.io.valid := Reg(reg_valid && ctrl.fma && ctrl.single)
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sfma.io.in1 := mem_rs1
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sfma.io.in2 := mem_rs2
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sfma.io.in3 := mem_rs3
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sfma.io.cmd := mem_ctrl.cmd
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sfma.io.rm := mem_rm
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val dfma = new rocketFPUDFMAPipe(dfma_latency-1)
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dfma.io.valid := Reg(reg_valid && ctrl.fma && !ctrl.single)
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dfma.io.in1 := mem_rs1
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dfma.io.in2 := mem_rs2
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dfma.io.in3 := mem_rs3
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dfma.io.cmd := mem_ctrl.cmd
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dfma.io.rm := mem_rm
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val wb_wrfsr_val = Reg(!io.ctrl.killm && mem_wrfsr_val, resetVal = Bool(false))
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val wb_toint_val = Reg(!io.ctrl.killm && mem_toint_val, resetVal = Bool(false))
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val wb_toint_exc = Reg(fpiu.io.exc)
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// writeback arbitration
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val wen = Reg(resetVal = Bits(0, dfma_latency-1))
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val wen = Reg(resetVal = Bits(0, dfma_latency))
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val winfo = Vec(dfma_latency-1) { Reg() { Bits() } }
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val mem_wen = Reg(resetVal = Bool(false))
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@ -478,8 +593,8 @@ class rocketFPU(sfma_latency: Int, dfma_latency: Int) extends Component
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Mux(ctrl.single, UFix(sfma_latency-1),
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UFix(dfma_latency-1)))
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val mem_fu_latency = Reg(ex_stage_fu_latency - UFix(1))
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val write_port_busy = ctrl.fastpipe && wen(fastpipe_latency-1) ||
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Bool(sfma_latency < dfma_latency) && ctrl.fma && ctrl.single && wen(sfma_latency-1) ||
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val write_port_busy = ctrl.fastpipe && wen(fastpipe_latency) ||
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Bool(sfma_latency < dfma_latency) && ctrl.fma && ctrl.single && wen(sfma_latency) ||
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mem_wen && mem_fu_latency === ex_stage_fu_latency
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mem_wen := reg_valid && !io.ctrl.killx && (ctrl.fma || ctrl.fastpipe)
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val ex_stage_wsrc = Cat(ctrl.fastpipe, ctrl.single)
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@ -503,15 +618,15 @@ class rocketFPU(sfma_latency: Int, dfma_latency: Int) extends Component
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}
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val wsrc = winfo(0)(1,0)
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val wdata = Mux(wsrc === UFix(0), UFix(0), // DFMA
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Mux(wsrc === UFix(1), UFix(0), // SFMA
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val wdata = Mux(wsrc === UFix(0), dfma.io.out, // DFMA
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Mux(wsrc === UFix(1), Cat(sp_msbs, sfma.io.out), // SFMA
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Mux(wsrc === UFix(2), fastpipe.io.out_d,
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fastpipe.io.out_s)))
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val wexc = Mux(wsrc === UFix(0), Bits(0), // DFMA
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Mux(wsrc === UFix(1), Bits(0), // SFMA
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Cat(sp_msbs, fastpipe.io.out_s))))
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val wexc = Mux(wsrc === UFix(0), dfma.io.exc, // DFMA
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Mux(wsrc === UFix(1), sfma.io.exc, // SFMA
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Mux(wsrc === UFix(2), fastpipe.io.exc_d,
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fastpipe.io.exc_s)))
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val waddr = winfo(0) >> UFix(2)
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val waddr = winfo(0).toUFix >> UFix(2)
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regfile.write(waddr, wdata, wen(0))
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when (wb_toint_val || wen(0)) {
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@ -531,4 +646,6 @@ class rocketFPU(sfma_latency: Int, dfma_latency: Int) extends Component
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io.ctrl.dec <> fp_decoder.io.sigs
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// we don't currently support round-max-magnitude (rm=4)
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io.ctrl.illegal_rm := ex_rm(2)
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io.ctrl.sboard_clr := wen(0) && !wsrc(1).toBool // only for FMA pipes
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io.ctrl.sboard_clra := waddr
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}
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@ -71,6 +71,12 @@ object LFSR16
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}
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}
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object ShiftRegister
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{
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def apply [T <: Data](n: Int, in: T): T =
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if (n > 0) Reg(apply(n-1, in)) else in
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}
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object Mux1H
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{
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//TODO: cloning in(0) is unsafe if other elements have different widths, but
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Block a user