riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Full conversion to params. Compiles but does not elaborate.

Browse Source
This commit is contained in:
Henry Cook
2014-08-08 12:23:02 -07:00
parent 4e6d69892d
commit 0dac9a7467
15 changed files with 500 additions and 560 deletions
Download Patch File Download Diff File Expand all files Collapse all files

91
rocket/src/main/scala/tile.scala
View File

@ -4,50 +4,46 @@ import Chisel._
import uncore._
import Util._
case class RocketConfiguration(tl: TileLinkConfiguration, as: AddressSpaceConfiguration,
icache: ICacheConfig, dcache: DCacheConfig,
rocc: Option[RocketConfiguration => RoCC] = None,
retireWidth: Int = 1,
vm: Boolean = true,
fastLoadWord: Boolean = true,
fastLoadByte: Boolean = false,
fastMulDiv: Boolean = true)
{
val dcacheReqTagBits = 7 // enforce compliance with require()
val xprlen = 64
val nxpr = 32
val nxprbits = log2Up(nxpr)
if (fastLoadByte) require(fastLoadWord)
}
case object NDCachePorts extends Field[Int]
case object NTilePorts extends Field[Int]
case object BuildRoCC extends Field[Option[() => RoCC]]
case object RetireWidth extends Field[Int]
case object UseVM extends Field[Boolean]
case object FastLoadWord extends Field[Boolean]
case object FastLoadByte extends Field[Boolean]
case object FastMulDiv extends Field[Boolean]
case object DcacheReqTagBits extends Field[Int]
case object XprLen extends Field[Int]
case object NXpr extends Field[Int]
case object NXprBits extends Field[Int]
case object RocketDCacheParams extends Field[PF]
case object RocketFrontendParams extends Field[PF]
class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module(_reset = resetSignal)
{
val memPorts = 2 + (!confIn.rocc.isEmpty).toInt // Number of ports to outer memory system from tile: 1 from I$, 1 from D$, maybe 1 from Rocc
val dcachePortId = 0
val icachePortId = 1
val roccPortId = 2
val dcachePorts = 2 + (!confIn.rocc.isEmpty).toInt // Number of ports into D$: 1 from core, 1 from PTW, maybe 1 from RoCC
implicit val tlConf = confIn.tl
implicit val lnConf = confIn.tl.ln
implicit val icConf = confIn.icache
implicit val dcConf = confIn.dcache.copy(reqtagbits = confIn.dcacheReqTagBits + log2Up(dcachePorts), databits = confIn.xprlen)
implicit val conf = confIn.copy(dcache = dcConf)
require(conf.retireWidth == 1) // for now...
class Tile(resetSignal: Bool = null) extends Module(_reset = resetSignal) {
if(params(FastLoadByte)) require(params(FastLoadWord))
require(params(RetireWidth) == 1) // for now...
val io = new Bundle {
val tilelink = new TileLinkIO
val host = new HTIFIO(lnConf.nClients)
val host = new HTIFIO
}
// Mimic client id extension done by UncachedTileLinkIOArbiter for Acquires from either client)
val core = Module(new Core)
val optionalRoCC = params(BuildRoCC)
params.alter(params(RocketFrontendParams)) // Used in icache, Core
val icache = Module(new Frontend)
params.alter(params(RocketDCacheParams)) // Used in dcache, PTW, RoCCm Core
val dcache = Module(new HellaCache)
val ptw = Module(new PTW(if (confIn.rocc.isEmpty) 2 else 5)) // 2 ports, 1 from I$, 1 from D$, maybe 3 from RoCC
val ptw = Module(new PTW(if(optionalRoCC.isEmpty) 2 else 5))
// 2 ports, 1 from I$, 1 from D$, maybe 3 from RoCC
val core = Module(new Core)
val dcacheArb = Module(new HellaCacheArbiter(dcachePorts))
dcacheArb.io.requestor(0) <> ptw.io.mem
dcacheArb.io.requestor(1) <> core.io.dmem
dcache.io.cpu <> dcacheArb.io.mem
val dcArb = Module(new HellaCacheArbiter(params(NDCachePorts)))
dcArb.io.requestor(0) <> ptw.io.mem
dcArb.io.requestor(1) <> core.io.dmem
dcArb.io.mem <> dcache.io.cpu
ptw.io.requestor(0) <> icache.io.cpu.ptw
ptw.io.requestor(1) <> dcache.io.cpu.ptw
@ -56,28 +52,31 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module
core.io.imem <> icache.io.cpu
core.io.ptw <> ptw.io.dpath
val memArb = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(memPorts))
memArb.io.in(dcachePortId) <> dcache.io.mem
memArb.io.in(icachePortId) <> icache.io.mem
val memArb = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(params(NTilePorts)))
val dcPortId = 0
memArb.io.in(dcPortId) <> dcache.io.mem
memArb.io.in(1) <> icache.io.mem
if (!conf.rocc.isEmpty) {
val rocc = Module((conf.rocc.get)(conf))
if(!optionalRoCC.isEmpty) {
val rocc = Module(optionalRoCC.get())
val dcIF = Module(new SimpleHellaCacheIF)
dcIF.io.requestor <> rocc.io.mem
core.io.rocc <> rocc.io
dcacheArb.io.requestor(2) <> dcIF.io.cache
memArb.io.in(roccPortId) <> rocc.io.imem
dcArb.io.requestor(2) <> dcIF.io.cache
memArb.io.in(2) <> rocc.io.imem
ptw.io.requestor(2) <> rocc.io.iptw
ptw.io.requestor(3) <> rocc.io.dptw
ptw.io.requestor(4) <> rocc.io.pptw
}
io.tilelink.acquire <> memArb.io.out.acquire
memArb.io.out.grant <> io.tilelink.grant
io.tilelink.grant <> memArb.io.out.grant
io.tilelink.finish <> memArb.io.out.finish
dcache.io.mem.probe <> io.tilelink.probe
// Probes and releases routed directly to coherent dcache
io.tilelink.probe <> dcache.io.mem.probe
// Mimic client id extension done by UncachedTileLinkIOArbiter for Acquires from either client)
io.tilelink.release.valid := dcache.io.mem.release.valid
dcache.io.mem.release.ready := io.tilelink.release.ready
io.tilelink.release.bits := dcache.io.mem.release.bits
io.tilelink.release.bits.payload.client_xact_id := Cat(dcache.io.mem.release.bits.payload.client_xact_id, UInt(dcachePortId, log2Up(memPorts))) // Mimic client id extension done by UncachedTileLinkIOArbiter for Acquires from either client)
io.tilelink.release.bits.payload.client_xact_id := Cat(dcache.io.mem.release.bits.payload.client_xact_id, UInt(dcPortId, log2Up(params(NTilePorts))))
}