riscv/rocket-chip
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Full conversion to params. Compiles but does not elaborate.

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This commit is contained in:
Henry Cook
2014-08-08 12:23:02 -07:00
parent 4e6d69892d
commit 0dac9a7467
15 changed files with 500 additions and 560 deletions
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31
rocket/src/main/scala/ptw.scala
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@ -4,39 +4,38 @@ import Chisel._
import uncore._
import Util._
class PTWResp()(implicit val conf: AddressSpaceConfiguration) extends BundleWithConf {
class PTWResp extends Bundle {
val error = Bool()
val ppn = UInt(width = conf.ppnBits)
val perm = Bits(width = conf.permBits)
val ppn = UInt(width = params(PPNBits))
val perm = Bits(width = params(PermBits))
}
class TLBPTWIO()(implicit val conf: AddressSpaceConfiguration) extends BundleWithConf {
val req = Decoupled(UInt(width = conf.vpnBits))
class TLBPTWIO extends Bundle {
val req = Decoupled(UInt(width = params(VPNBits)))
val resp = Valid(new PTWResp).flip
val status = new Status().asInput
val invalidate = Bool(INPUT)
val sret = Bool(INPUT)
}
class DatapathPTWIO()(implicit val conf: AddressSpaceConfiguration) extends BundleWithConf {
val ptbr = UInt(INPUT, conf.paddrBits)
class DatapathPTWIO extends Bundle {
val ptbr = UInt(INPUT, params(PAddrBits))
val invalidate = Bool(INPUT)
val sret = Bool(INPUT)
val status = new Status().asInput
}
class PTW(n: Int)(implicit conf: RocketConfiguration) extends Module
class PTW(n: Int) extends Module
{
implicit val as = conf.as
val io = new Bundle {
val requestor = Vec.fill(n){new TLBPTWIO}.flip
val mem = new HellaCacheIO()(conf.dcache)
val mem = new HellaCacheIO
val dpath = new DatapathPTWIO
}
val levels = 3
val bitsPerLevel = conf.as.vpnBits/levels
require(conf.as.vpnBits == levels * bitsPerLevel)
val bitsPerLevel = params(VPNBits)/levels
require(params(VPNBits) == levels * bitsPerLevel)
val s_ready :: s_req :: s_wait :: s_done :: s_error :: Nil = Enum(UInt(), 5)
val state = Reg(init=s_ready)
@ -48,14 +47,14 @@ class PTW(n: Int)(implicit conf: RocketConfiguration) extends Module
val vpn_idx = Vec((0 until levels).map(i => (r_req_vpn >> (levels-i-1)*bitsPerLevel)(bitsPerLevel-1,0)))(count)
val arb = Module(new RRArbiter(UInt(width = conf.as.vpnBits), n))
val arb = Module(new RRArbiter(UInt(width = params(VPNBits)), n))
arb.io.in <> io.requestor.map(_.req)
arb.io.out.ready := state === s_ready
when (arb.io.out.fire()) {
r_req_vpn := arb.io.out.bits
r_req_dest := arb.io.chosen
r_pte := Cat(io.dpath.ptbr(conf.as.paddrBits-1,conf.as.pgIdxBits), io.mem.resp.bits.data(conf.as.pgIdxBits-1,0))
r_pte := Cat(io.dpath.ptbr(params(PAddrBits)-1,params(PgIdxBits)), io.mem.resp.bits.data(params(PgIdxBits)-1,0))
}
when (io.mem.resp.valid) {
@ -66,13 +65,13 @@ class PTW(n: Int)(implicit conf: RocketConfiguration) extends Module
io.mem.req.bits.phys := Bool(true)
io.mem.req.bits.cmd := M_XRD
io.mem.req.bits.typ := MT_D
io.mem.req.bits.addr := Cat(r_pte(conf.as.paddrBits-1,conf.as.pgIdxBits), vpn_idx).toUInt << log2Up(conf.xprlen/8)
io.mem.req.bits.addr := Cat(r_pte(params(PAddrBits)-1,params(PgIdxBits)), vpn_idx).toUInt << log2Up(params(XprLen)/8)
io.mem.req.bits.kill := Bool(false)
val resp_val = state === s_done || state === s_error
val resp_err = state === s_error || state === s_wait
val r_resp_ppn = io.mem.req.bits.addr >> conf.as.pgIdxBits
val r_resp_ppn = io.mem.req.bits.addr >> params(PgIdxBits)
val resp_ppn = Vec((0 until levels-1).map(i => Cat(r_resp_ppn >> bitsPerLevel*(levels-i-1), r_req_vpn(bitsPerLevel*(levels-i-1)-1,0))) :+ r_resp_ppn)(count)
for (i <- 0 until io.requestor.size) {