Full conversion to params. Compiles but does not elaborate.
This commit is contained in:
Henry Cook
@ -4,47 +4,25 @@ import Chisel._
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import uncore._
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import Util._
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case class DCacheConfig(val sets: Int, val ways: Int,
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nmshr: Int, nrpq: Int, nsdq: Int, ntlb: Int,
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val tl: TileLinkConfiguration,
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val as: AddressSpaceConfiguration,
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reqtagbits: Int, databits: Int,
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rowwords: Int = 2,
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code: Code = new IdentityCode,
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narrowRead: Boolean = true) extends CacheConfig {
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def states = tl.co.nClientStates
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def lines = sets*ways
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def dm = ways == 1
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def offbits = log2Up(tl.dataBits/8)
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def ppnbits = as.ppnBits
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def vpnbits = as.vpnBits
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def pgidxbits = as.pgIdxBits
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def maxaddrbits = ppnbits.max(vpnbits+1) + pgidxbits
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def paddrbits = as.paddrBits
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def lineaddrbits = paddrbits - offbits
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def idxbits = log2Up(sets)
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def waybits = log2Up(ways)
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def untagbits = offbits + idxbits
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def tagbits = lineaddrbits - idxbits
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def databytes = databits/8
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def wordoffbits = log2Up(databytes)
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def rowbits = rowwords*databits
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def rowbytes = rowwords*databytes
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def rowoffbits = log2Up(rowbytes)
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def refillcycles = tl.dataBits/(rowbits)
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def isNarrowRead = narrowRead && databits*ways % rowbits == 0
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val statebits = log2Up(states)
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val encdatabits = code.width(databits)
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val encrowbits = rowwords*encdatabits
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val lrsc_cycles = 32 // ISA requires 16-insn LRSC sequences to succeed
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require(states > 0)
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require(isPow2(sets))
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require(isPow2(ways)) // TODO: relax this
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require(rowbits <= tl.dataBits)
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require(lineaddrbits == tl.addrBits)
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require(untagbits <= pgidxbits)
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}
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//Knobs
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case object StoreDataQueueDepth extends Field[Int]
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case object ReplayQueueDepth extends Field[Int]
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case object NMSHRs extends Field[Int]
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case object NTLBEntries extends Field[Int]
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case object CoreReqTagBits extends Field[Int]
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case object CoreDataBits extends Field[Int]
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case object RowWords extends Field[Int]
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case object ECCCode extends Field[Code]
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//Derived
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case object MaxAddrBits extends Field[Int]
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case object CoreDataBytes extends Field[Int]
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case object WordOffBits extends Field[Int]
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case object RowBytes extends Field[Int]
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case object RowOffBits extends Field[Int]
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case object DoNarrowRead extends Field[Int]
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case object EncDataBits extends Field[Int]
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case object EncRowBits extends Field[Int]
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case object LRSCCycles extends Field[Int]
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class StoreGen(typ: Bits, addr: Bits, dat: Bits)
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{
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@ -78,69 +56,68 @@ class LoadGen(typ: Bits, addr: Bits, dat: Bits, zero: Bool)
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val byte = Cat(Mux(zero || t.byte, Fill(56, sign && byteShift(7)), half(63,8)), byteShift)
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}
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class MSHRReq(implicit val cacheconf: DCacheConfig) extends HellaCacheReq {
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class MSHRReq extends HellaCacheReq {
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val tag_match = Bool()
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val old_meta = new L1Metadata
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val way_en = Bits(width = cacheconf.ways)
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val way_en = Bits(width = params(NWays))
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}
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class Replay(implicit conf: DCacheConfig) extends HellaCacheReq {
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val sdq_id = UInt(width = log2Up(conf.nsdq))
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class Replay extends HellaCacheReq {
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val sdq_id = UInt(width = log2Up(params(StoreDataQueueDepth)))
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}
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class DataReadReq(implicit val conf: DCacheConfig) extends BundleWithConf {
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val way_en = Bits(width = conf.ways)
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val addr = Bits(width = conf.untagbits)
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class DataReadReq extends Bundle {
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val way_en = Bits(width = params(NWays))
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val addr = Bits(width = params(UntagBits))
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}
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class DataWriteReq(implicit conf: DCacheConfig) extends DataReadReq {
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val wmask = Bits(width = conf.rowwords)
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val data = Bits(width = conf.encrowbits)
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class DataWriteReq extends DataReadReq {
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val wmask = Bits(width = params(RowWords))
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val data = Bits(width = params(EncRowBits))
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}
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class L1MetaReadReq(implicit conf: DCacheConfig) extends MetaReadReq {
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val tag = Bits(width = conf.tagbits)
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class L1MetaReadReq extends MetaReadReq {
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val tag = Bits(width = params(TagBits))
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}
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class L1MetaWriteReq(implicit conf: DCacheConfig) extends
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class L1MetaWriteReq extends
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MetaWriteReq[L1Metadata](new L1Metadata)
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object L1Metadata {
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def apply(tag: Bits, coh: ClientMetadata)(implicit conf: DCacheConfig) = {
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def apply(tag: Bits, coh: ClientMetadata) = {
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val meta = new L1Metadata
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meta.tag := tag
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meta.coh := coh
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meta
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}
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}
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class L1Metadata(implicit val conf: DCacheConfig) extends Metadata {
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val coh = conf.tl.co.clientMetadataOnFlush.clone
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class L1Metadata extends Metadata {
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val coh = params(TLCoherence).clientMetadataOnFlush.clone
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}
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class InternalProbe(implicit conf: TileLinkConfiguration) extends Probe()(conf)
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with HasClientTransactionId
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class InternalProbe extends Probe with HasClientTransactionId
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class WritebackReq(implicit val conf: DCacheConfig) extends BundleWithConf {
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val tag = Bits(width = conf.tagbits)
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val idx = Bits(width = conf.idxbits)
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val way_en = Bits(width = conf.ways)
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val client_xact_id = Bits(width = conf.tl.clientXactIdBits)
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val master_xact_id = Bits(width = conf.tl.masterXactIdBits)
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val r_type = UInt(width = conf.tl.co.releaseTypeWidth)
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class WritebackReq extends Bundle {
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val tag = Bits(width = params(TagBits))
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val idx = Bits(width = params(IdxBits))
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val way_en = Bits(width = params(NWays))
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val client_xact_id = Bits(width = params(TLClientXactIdBits))
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val master_xact_id = Bits(width = params(TLMasterXactIdBits))
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val r_type = UInt(width = params(TLCoherence).releaseTypeWidth)
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}
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class MSHR(id: Int)(implicit conf: DCacheConfig) extends Module {
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implicit val (tl, ln) = (conf.tl, conf.tl.ln)
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class MSHR(id: Int) extends Module {
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val co = params(TLCoherence)
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val io = new Bundle {
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val req_pri_val = Bool(INPUT)
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val req_pri_rdy = Bool(OUTPUT)
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val req_sec_val = Bool(INPUT)
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val req_sec_rdy = Bool(OUTPUT)
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val req_bits = new MSHRReq().asInput
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val req_sdq_id = UInt(INPUT, log2Up(conf.nsdq))
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val req_sdq_id = UInt(INPUT, log2Up(params(StoreDataQueueDepth)))
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val idx_match = Bool(OUTPUT)
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val tag = Bits(OUTPUT, conf.tagbits)
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val tag = Bits(OUTPUT, params(TagBits))
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val mem_req = Decoupled(new Acquire)
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val mem_resp = new DataWriteReq().asOutput
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@ -158,25 +135,25 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Module {
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val acquire_type = Reg(UInt())
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val release_type = Reg(UInt())
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val line_state = Reg(new ClientMetadata()(tl.co))
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val refill_count = Reg(UInt(width = log2Up(conf.refillcycles))) // TODO: zero-width wire
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val line_state = Reg(new ClientMetadata()(co))
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val refill_count = Reg(UInt(width = log2Up(params(RefillCycles)))) // TODO: zero-width wire
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val req = Reg(new MSHRReq())
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val req_cmd = io.req_bits.cmd
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val req_idx = req.addr(conf.untagbits-1,conf.offbits)
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val idx_match = req_idx === io.req_bits.addr(conf.untagbits-1,conf.offbits)
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val sec_rdy = idx_match && (state === s_wb_req || state === s_wb_resp || state === s_meta_clear || (state === s_refill_req || state === s_refill_resp) && !tl.co.needsTransactionOnSecondaryMiss(req_cmd, io.mem_req.bits))
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val req_idx = req.addr(params(UntagBits)-1,params(OffBits))
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val idx_match = req_idx === io.req_bits.addr(params(UntagBits)-1,params(OffBits))
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val sec_rdy = idx_match && (state === s_wb_req || state === s_wb_resp || state === s_meta_clear || (state === s_refill_req || state === s_refill_resp) && !co.needsTransactionOnSecondaryMiss(req_cmd, io.mem_req.bits))
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require(isPow2(conf.refillcycles))
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require(isPow2(params(RefillCycles)))
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val reply = io.mem_grant.valid && io.mem_grant.bits.payload.client_xact_id === UInt(id)
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val refill_done = reply && (if(conf.refillcycles > 1) refill_count.andR else Bool(true))
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val refill_done = reply && (if(params(RefillCycles) > 1) refill_count.andR else Bool(true))
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val wb_done = reply && (state === s_wb_resp)
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val meta_on_flush = tl.co.clientMetadataOnFlush
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val meta_on_grant = tl.co.clientMetadataOnGrant(io.mem_grant.bits.payload, io.mem_req.bits)
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val meta_on_hit = tl.co.clientMetadataOnHit(req_cmd, io.req_bits.old_meta.coh)
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val meta_on_flush = co.clientMetadataOnFlush
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val meta_on_grant = co.clientMetadataOnGrant(io.mem_grant.bits.payload, io.mem_req.bits)
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val meta_on_hit = co.clientMetadataOnHit(req_cmd, io.req_bits.old_meta.coh)
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val rpq = Module(new Queue(new Replay, conf.nrpq))
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val rpq = Module(new Queue(new Replay, params(ReplayQueueDepth)))
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rpq.io.enq.valid := (io.req_pri_val && io.req_pri_rdy || io.req_sec_val && sec_rdy) && !isPrefetch(req_cmd)
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rpq.io.enq.bits := io.req_bits
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rpq.io.enq.bits.sdq_id := io.req_sdq_id
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@ -195,7 +172,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Module {
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when (state === s_refill_resp) {
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when (refill_done) { state := s_meta_write_req }
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when (reply) {
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if(conf.refillcycles > 1) refill_count := refill_count + UInt(1)
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if(params(RefillCycles) > 1) refill_count := refill_count + UInt(1)
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line_state := meta_on_grant
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}
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}
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@ -213,29 +190,29 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Module {
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}
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when (io.req_sec_val && io.req_sec_rdy) { // s_wb_req, s_wb_resp, s_refill_req
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acquire_type := tl.co.getAcquireTypeOnSecondaryMiss(req_cmd, meta_on_flush, io.mem_req.bits)
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acquire_type := co.getAcquireTypeOnSecondaryMiss(req_cmd, meta_on_flush, io.mem_req.bits)
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}
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when (io.req_pri_val && io.req_pri_rdy) {
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line_state := meta_on_flush
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refill_count := UInt(0)
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acquire_type := tl.co.getAcquireTypeOnPrimaryMiss(req_cmd, meta_on_flush)
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release_type := tl.co.getReleaseTypeOnVoluntaryWriteback() //TODO downgrades etc
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acquire_type := co.getAcquireTypeOnPrimaryMiss(req_cmd, meta_on_flush)
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release_type := co.getReleaseTypeOnVoluntaryWriteback() //TODO downgrades etc
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req := io.req_bits
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when (io.req_bits.tag_match) {
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when (tl.co.isHit(req_cmd, io.req_bits.old_meta.coh)) { // set dirty bit
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when (co.isHit(req_cmd, io.req_bits.old_meta.coh)) { // set dirty bit
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state := s_meta_write_req
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line_state := meta_on_hit
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}.otherwise { // upgrade permissions
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state := s_refill_req
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}
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}.otherwise { // writback if necessary and refill
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state := Mux(tl.co.needsWriteback(io.req_bits.old_meta.coh), s_wb_req, s_meta_clear)
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state := Mux(co.needsWriteback(io.req_bits.old_meta.coh), s_wb_req, s_meta_clear)
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}
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}
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val ackq = Module(new Queue(new LogicalNetworkIO(new Finish), 1))
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ackq.io.enq.valid := (wb_done || refill_done) && tl.co.requiresAckForGrant(io.mem_grant.bits.payload.g_type)
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ackq.io.enq.valid := (wb_done || refill_done) && co.requiresAckForGrant(io.mem_grant.bits.payload.g_type)
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ackq.io.enq.bits.payload.master_xact_id := io.mem_grant.bits.payload.master_xact_id
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ackq.io.enq.bits.header.dst := io.mem_grant.bits.header.src
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val can_finish = state === s_invalid || state === s_refill_req || state === s_refill_resp
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@ -245,8 +222,8 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Module {
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io.idx_match := (state != s_invalid) && idx_match
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io.mem_resp := req
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io.mem_resp.addr := (if(conf.refillcycles > 1) Cat(req_idx, refill_count) else req_idx) << conf.rowoffbits
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io.tag := req.addr >> conf.untagbits
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io.mem_resp.addr := (if(params(RefillCycles) > 1) Cat(req_idx, refill_count) else req_idx) << params(RowOffBits)
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io.tag := req.addr >> params(UntagBits)
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io.req_pri_rdy := state === s_invalid
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io.req_sec_rdy := sec_rdy && rpq.io.enq.ready
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@ -267,7 +244,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Module {
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io.wb_req.bits.way_en := req.way_en
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io.wb_req.bits.client_xact_id := Bits(id)
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io.wb_req.bits.master_xact_id := Bits(0) // DNC
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io.wb_req.bits.r_type := tl.co.getReleaseTypeOnVoluntaryWriteback()
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io.wb_req.bits.r_type := co.getReleaseTypeOnVoluntaryWriteback()
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io.mem_req.valid := state === s_refill_req && ackq.io.enq.ready
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io.mem_req.bits.a_type := acquire_type
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@ -282,7 +259,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Module {
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io.replay.valid := state === s_drain_rpq && rpq.io.deq.valid
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io.replay.bits := rpq.io.deq.bits
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io.replay.bits.phys := Bool(true)
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io.replay.bits.addr := Cat(io.tag, req_idx, rpq.io.deq.bits.addr(conf.offbits-1,0)).toUInt
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io.replay.bits.addr := Cat(io.tag, req_idx, rpq.io.deq.bits.addr(params(OffBits)-1,0)).toUInt
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when (!io.meta_read.ready) {
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rpq.io.deq.ready := Bool(false)
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@ -290,8 +267,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Module {
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}
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}
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class MSHRFile(implicit conf: DCacheConfig) extends Module {
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implicit val (tl, ln) = (conf.tl, conf.tl.ln)
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class MSHRFile extends Module {
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val io = new Bundle {
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val req = Decoupled(new MSHRReq).flip
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val secondary_miss = Bool(OUTPUT)
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@ -309,26 +285,26 @@ class MSHRFile(implicit conf: DCacheConfig) extends Module {
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val fence_rdy = Bool(OUTPUT)
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}
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val sdq_val = Reg(init=Bits(0, conf.nsdq))
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val sdq_alloc_id = PriorityEncoder(~sdq_val(conf.nsdq-1,0))
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val sdq_val = Reg(init=Bits(0, params(StoreDataQueueDepth)))
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val sdq_alloc_id = PriorityEncoder(~sdq_val(params(StoreDataQueueDepth)-1,0))
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val sdq_rdy = !sdq_val.andR
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val sdq_enq = io.req.valid && io.req.ready && isWrite(io.req.bits.cmd)
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val sdq = Mem(io.req.bits.data, conf.nsdq)
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val sdq = Mem(io.req.bits.data, params(StoreDataQueueDepth))
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when (sdq_enq) { sdq(sdq_alloc_id) := io.req.bits.data }
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val idxMatch = Vec.fill(conf.nmshr){Bool()}
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val tagList = Vec.fill(conf.nmshr){Bits()}
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val tag_match = Mux1H(idxMatch, tagList) === io.req.bits.addr >> conf.untagbits
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val idxMatch = Vec.fill(params(NMSHRs)){Bool()}
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val tagList = Vec.fill(params(NMSHRs)){Bits()}
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val tag_match = Mux1H(idxMatch, tagList) === io.req.bits.addr >> params(UntagBits)
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val wbTagList = Vec.fill(conf.nmshr){Bits()}
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val memRespMux = Vec.fill(conf.nmshr){new DataWriteReq}
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val meta_read_arb = Module(new Arbiter(new L1MetaReadReq, conf.nmshr))
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val meta_write_arb = Module(new Arbiter(new L1MetaWriteReq, conf.nmshr))
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val mem_req_arb = Module(new Arbiter(new Acquire, conf.nmshr))
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val mem_finish_arb = Module(new Arbiter(new LogicalNetworkIO(new Finish), conf.nmshr))
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val wb_req_arb = Module(new Arbiter(new WritebackReq, conf.nmshr))
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val replay_arb = Module(new Arbiter(new Replay, conf.nmshr))
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val alloc_arb = Module(new Arbiter(Bool(), conf.nmshr))
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val wbTagList = Vec.fill(params(NMSHRs)){Bits()}
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val memRespMux = Vec.fill(params(NMSHRs)){new DataWriteReq}
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val meta_read_arb = Module(new Arbiter(new L1MetaReadReq, params(NMSHRs)))
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val meta_write_arb = Module(new Arbiter(new L1MetaWriteReq, params(NMSHRs)))
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val mem_req_arb = Module(new Arbiter(new Acquire, params(NMSHRs)))
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val mem_finish_arb = Module(new Arbiter(new LogicalNetworkIO(new Finish), params(NMSHRs)))
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val wb_req_arb = Module(new Arbiter(new WritebackReq, params(NMSHRs)))
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val replay_arb = Module(new Arbiter(new Replay, params(NMSHRs)))
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val alloc_arb = Module(new Arbiter(Bool(), params(NMSHRs)))
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var idx_match = Bool(false)
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var pri_rdy = Bool(false)
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@ -337,7 +313,7 @@ class MSHRFile(implicit conf: DCacheConfig) extends Module {
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io.fence_rdy := true
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io.probe_rdy := true
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for (i <- 0 to conf.nmshr-1) {
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for (i <- 0 until params(NMSHRs)) {
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val mshr = Module(new MSHR(i))
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idxMatch(i) := mshr.io.idx_match
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@ -386,26 +362,25 @@ class MSHRFile(implicit conf: DCacheConfig) extends Module {
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io.replay <> replay_arb.io.out
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when (io.replay.valid || sdq_enq) {
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sdq_val := sdq_val & ~(UIntToOH(io.replay.bits.sdq_id) & Fill(conf.nsdq, free_sdq)) |
|
||||
PriorityEncoderOH(~sdq_val(conf.nsdq-1,0)) & Fill(conf.nsdq, sdq_enq)
|
||||
sdq_val := sdq_val & ~(UIntToOH(io.replay.bits.sdq_id) & Fill(params(StoreDataQueueDepth), free_sdq)) |
|
||||
PriorityEncoderOH(~sdq_val(params(StoreDataQueueDepth)-1,0)) & Fill(params(StoreDataQueueDepth), sdq_enq)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
class WritebackUnit(implicit conf: DCacheConfig) extends Module {
|
||||
implicit val tl = conf.tl
|
||||
class WritebackUnit extends Module {
|
||||
val io = new Bundle {
|
||||
val req = Decoupled(new WritebackReq()).flip
|
||||
val meta_read = Decoupled(new L1MetaReadReq)
|
||||
val data_req = Decoupled(new DataReadReq())
|
||||
val data_resp = Bits(INPUT, conf.encrowbits)
|
||||
val data_resp = Bits(INPUT, params(EncRowBits))
|
||||
val release = Decoupled(new Release)
|
||||
}
|
||||
|
||||
val active = Reg(init=Bool(false))
|
||||
val r1_data_req_fired = Reg(init=Bool(false))
|
||||
val r2_data_req_fired = Reg(init=Bool(false))
|
||||
val cnt = Reg(init = UInt(0, width = log2Up(conf.refillcycles+1)))
|
||||
val cnt = Reg(init = UInt(0, width = log2Up(params(RefillCycles)+1)))
|
||||
val req = Reg(new WritebackReq)
|
||||
|
||||
io.release.valid := false
|
||||
@ -416,8 +391,8 @@ class WritebackUnit(implicit conf: DCacheConfig) extends Module {
|
||||
r1_data_req_fired := true
|
||||
cnt := cnt + 1
|
||||
}
|
||||
if(conf.refillcycles > 1) { // Coalescing buffer inserted
|
||||
when (!r1_data_req_fired && !r2_data_req_fired && cnt === conf.refillcycles) {
|
||||
if(params(RefillCycles) > 1) { // Coalescing buffer inserted
|
||||
when (!r1_data_req_fired && !r2_data_req_fired && cnt === params(RefillCycles)) {
|
||||
io.release.valid := true
|
||||
active := !io.release.ready
|
||||
}
|
||||
@ -440,7 +415,7 @@ class WritebackUnit(implicit conf: DCacheConfig) extends Module {
|
||||
req := io.req.bits
|
||||
}
|
||||
|
||||
val fire = active && cnt < UInt(conf.refillcycles)
|
||||
val fire = active && cnt < UInt(params(RefillCycles))
|
||||
io.req.ready := !active
|
||||
|
||||
// We reissue the meta read as it sets up the muxing for s2_data_muxed
|
||||
@ -450,20 +425,20 @@ class WritebackUnit(implicit conf: DCacheConfig) extends Module {
|
||||
|
||||
io.data_req.valid := fire
|
||||
io.data_req.bits.way_en := req.way_en
|
||||
if(conf.refillcycles > 1) {
|
||||
io.data_req.bits.addr := Cat(req.idx, cnt(log2Up(conf.refillcycles)-1,0)) << conf.rowoffbits
|
||||
if(params(RefillCycles) > 1) {
|
||||
io.data_req.bits.addr := Cat(req.idx, cnt(log2Up(params(RefillCycles))-1,0)) << params(RowOffBits)
|
||||
} else {
|
||||
io.data_req.bits.addr := req.idx << conf.rowoffbits
|
||||
io.data_req.bits.addr := req.idx << params(RowOffBits)
|
||||
}
|
||||
|
||||
io.release.bits.r_type := req.r_type
|
||||
io.release.bits.addr := Cat(req.tag, req.idx).toUInt
|
||||
io.release.bits.client_xact_id := req.client_xact_id
|
||||
io.release.bits.master_xact_id := req.master_xact_id
|
||||
if(conf.refillcycles > 1) {
|
||||
if(params(RefillCycles) > 1) {
|
||||
val data_buf = Reg(Bits())
|
||||
when(active && r2_data_req_fired) {
|
||||
data_buf := Cat(io.data_resp, data_buf(conf.refillcycles*conf.encrowbits-1, conf.encrowbits))
|
||||
data_buf := Cat(io.data_resp, data_buf(params(RefillCycles)*params(EncRowBits)-1, params(EncRowBits)))
|
||||
}
|
||||
io.release.bits.data := data_buf
|
||||
} else {
|
||||
@ -472,22 +447,22 @@ class WritebackUnit(implicit conf: DCacheConfig) extends Module {
|
||||
|
||||
}
|
||||
|
||||
class ProbeUnit(implicit conf: DCacheConfig) extends Module {
|
||||
implicit val tl = conf.tl
|
||||
class ProbeUnit extends Module {
|
||||
val co = params(TLCoherence)
|
||||
val io = new Bundle {
|
||||
val req = Decoupled(new InternalProbe).flip
|
||||
val rep = Decoupled(new Release)
|
||||
val meta_read = Decoupled(new L1MetaReadReq)
|
||||
val meta_write = Decoupled(new L1MetaWriteReq)
|
||||
val wb_req = Decoupled(new WritebackReq)
|
||||
val way_en = Bits(INPUT, conf.ways)
|
||||
val way_en = Bits(INPUT, params(NWays))
|
||||
val mshr_rdy = Bool(INPUT)
|
||||
val line_state = new ClientMetadata()(tl.co).asInput
|
||||
val line_state = new ClientMetadata()(co).asInput
|
||||
}
|
||||
|
||||
val s_reset :: s_invalid :: s_meta_read :: s_meta_resp :: s_mshr_req :: s_release :: s_writeback_req :: s_writeback_resp :: s_meta_write :: Nil = Enum(UInt(), 9)
|
||||
val state = Reg(init=s_invalid)
|
||||
val line_state = Reg(tl.co.clientMetadataOnFlush.clone)
|
||||
val line_state = Reg(co.clientMetadataOnFlush.clone)
|
||||
val way_en = Reg(Bits())
|
||||
val req = Reg(new InternalProbe)
|
||||
val hit = way_en.orR
|
||||
@ -504,7 +479,7 @@ class ProbeUnit(implicit conf: DCacheConfig) extends Module {
|
||||
when (state === s_release && io.rep.ready) {
|
||||
state := s_invalid
|
||||
when (hit) {
|
||||
state := Mux(tl.co.needsWriteback(line_state), s_writeback_req, s_meta_write)
|
||||
state := Mux(co.needsWriteback(line_state), s_writeback_req, s_meta_write)
|
||||
}
|
||||
}
|
||||
when (state === s_mshr_req) {
|
||||
@ -528,65 +503,65 @@ class ProbeUnit(implicit conf: DCacheConfig) extends Module {
|
||||
}
|
||||
|
||||
io.req.ready := state === s_invalid
|
||||
io.rep.valid := state === s_release && !(hit && tl.co.needsWriteback(line_state))
|
||||
io.rep.bits := Release(tl.co.getReleaseTypeOnProbe(req, Mux(hit, line_state, tl.co.clientMetadataOnFlush)), req.addr, req.client_xact_id, req.master_xact_id)
|
||||
io.rep.valid := state === s_release && !(hit && co.needsWriteback(line_state))
|
||||
io.rep.bits := Release(co.getReleaseTypeOnProbe(req, Mux(hit, line_state, co.clientMetadataOnFlush)), req.addr, req.client_xact_id, req.master_xact_id)
|
||||
|
||||
io.meta_read.valid := state === s_meta_read
|
||||
io.meta_read.bits.idx := req.addr
|
||||
io.meta_read.bits.tag := req.addr >> conf.idxbits
|
||||
io.meta_read.bits.tag := req.addr >> params(IdxBits)
|
||||
|
||||
io.meta_write.valid := state === s_meta_write
|
||||
io.meta_write.bits.way_en := way_en
|
||||
io.meta_write.bits.idx := req.addr
|
||||
io.meta_write.bits.data.coh := tl.co.clientMetadataOnProbe(req, line_state)
|
||||
io.meta_write.bits.data.tag := req.addr >> UInt(conf.idxbits)
|
||||
io.meta_write.bits.data.coh := co.clientMetadataOnProbe(req, line_state)
|
||||
io.meta_write.bits.data.tag := req.addr >> UInt(params(IdxBits))
|
||||
|
||||
io.wb_req.valid := state === s_writeback_req
|
||||
io.wb_req.bits.way_en := way_en
|
||||
io.wb_req.bits.idx := req.addr
|
||||
io.wb_req.bits.tag := req.addr >> UInt(conf.idxbits)
|
||||
io.wb_req.bits.r_type := tl.co.getReleaseTypeOnProbe(req, Mux(hit, line_state, tl.co.clientMetadataOnFlush))
|
||||
io.wb_req.bits.tag := req.addr >> UInt(params(IdxBits))
|
||||
io.wb_req.bits.r_type := co.getReleaseTypeOnProbe(req, Mux(hit, line_state, co.clientMetadataOnFlush))
|
||||
io.wb_req.bits.client_xact_id := req.client_xact_id
|
||||
io.wb_req.bits.master_xact_id := req.master_xact_id
|
||||
}
|
||||
|
||||
class DataArray(implicit conf: DCacheConfig) extends Module {
|
||||
class DataArray extends Module {
|
||||
val io = new Bundle {
|
||||
val read = Decoupled(new DataReadReq).flip
|
||||
val write = Decoupled(new DataWriteReq).flip
|
||||
val resp = Vec.fill(conf.ways){Bits(OUTPUT, conf.encrowbits)}
|
||||
val resp = Vec.fill(params(NWays)){Bits(OUTPUT, params(EncRowBits))}
|
||||
}
|
||||
|
||||
val waddr = io.write.bits.addr >> conf.rowoffbits
|
||||
val raddr = io.read.bits.addr >> conf.rowoffbits
|
||||
val waddr = io.write.bits.addr >> params(RowOffBits)
|
||||
val raddr = io.read.bits.addr >> params(RowOffBits)
|
||||
|
||||
if (conf.isNarrowRead) {
|
||||
for (w <- 0 until conf.ways by conf.rowwords) {
|
||||
val wway_en = io.write.bits.way_en(w+conf.rowwords-1,w)
|
||||
val rway_en = io.read.bits.way_en(w+conf.rowwords-1,w)
|
||||
val resp = Vec.fill(conf.rowwords){Bits(width = conf.encrowbits)}
|
||||
if (params(DoNarrowRead)) {
|
||||
for (w <- 0 until params(NWays) by params(RowWords)) {
|
||||
val wway_en = io.write.bits.way_en(w+params(RowWords)-1,w)
|
||||
val rway_en = io.read.bits.way_en(w+params(RowWords)-1,w)
|
||||
val resp = Vec.fill(params(RowWords)){Bits(width = params(EncRowBits))}
|
||||
val r_raddr = RegEnable(io.read.bits.addr, io.read.valid)
|
||||
for (p <- 0 until resp.size) {
|
||||
val array = Mem(Bits(width=conf.encrowbits), conf.sets*conf.refillcycles, seqRead = true)
|
||||
val array = Mem(Bits(width=params(EncRowBits)), params(NSets)*params(RefillCycles), seqRead = true)
|
||||
when (wway_en.orR && io.write.valid && io.write.bits.wmask(p)) {
|
||||
val data = Fill(conf.rowwords, io.write.bits.data(conf.encdatabits*(p+1)-1,conf.encdatabits*p))
|
||||
val mask = FillInterleaved(conf.encdatabits, wway_en)
|
||||
val data = Fill(params(RowWords), io.write.bits.data(params(EncDataBits)*(p+1)-1,params(EncDataBits)*p))
|
||||
val mask = FillInterleaved(params(EncDataBits), wway_en)
|
||||
array.write(waddr, data, mask)
|
||||
}
|
||||
resp(p) := array(RegEnable(raddr, rway_en.orR && io.read.valid))
|
||||
}
|
||||
for (dw <- 0 until conf.rowwords) {
|
||||
val r = Vec(resp.map(_(conf.encdatabits*(dw+1)-1,conf.encdatabits*dw)))
|
||||
for (dw <- 0 until params(RowWords)) {
|
||||
val r = Vec(resp.map(_(params(EncDataBits)*(dw+1)-1,params(EncDataBits)*dw)))
|
||||
val resp_mux =
|
||||
if (r.size == 1) r
|
||||
else Vec(r(r_raddr(conf.rowoffbits-1,conf.wordoffbits)), r.tail:_*)
|
||||
else Vec(r(r_raddr(params(RowOffBits)-1,params(WordOffBits))), r.tail:_*)
|
||||
io.resp(w+dw) := resp_mux.toBits
|
||||
}
|
||||
}
|
||||
} else {
|
||||
val wmask = FillInterleaved(conf.encdatabits, io.write.bits.wmask)
|
||||
for (w <- 0 until conf.ways) {
|
||||
val array = Mem(Bits(width=conf.encrowbits), conf.sets*conf.refillcycles, seqRead = true)
|
||||
val wmask = FillInterleaved(params(EncDataBits), io.write.bits.wmask)
|
||||
for (w <- 0 until params(NWays)) {
|
||||
val array = Mem(Bits(width=params(EncRowBits)), params(NSets)*params(RefillCycles), seqRead = true)
|
||||
when (io.write.bits.way_en(w) && io.write.valid) {
|
||||
array.write(waddr, io.write.bits.data, wmask)
|
||||
}
|
||||
@ -598,17 +573,17 @@ class DataArray(implicit conf: DCacheConfig) extends Module {
|
||||
io.write.ready := Bool(true)
|
||||
}
|
||||
|
||||
class AMOALU(implicit conf: DCacheConfig) extends Module {
|
||||
class AMOALU extends Module {
|
||||
val io = new Bundle {
|
||||
val addr = Bits(INPUT, conf.offbits)
|
||||
val addr = Bits(INPUT, params(OffBits))
|
||||
val cmd = Bits(INPUT, 4)
|
||||
val typ = Bits(INPUT, 3)
|
||||
val lhs = Bits(INPUT, conf.databits)
|
||||
val rhs = Bits(INPUT, conf.databits)
|
||||
val out = Bits(OUTPUT, conf.databits)
|
||||
val lhs = Bits(INPUT, params(CoreDataBits))
|
||||
val rhs = Bits(INPUT, params(CoreDataBits))
|
||||
val out = Bits(OUTPUT, params(CoreDataBits))
|
||||
}
|
||||
|
||||
require(conf.databits == 64)
|
||||
require(params(CoreDataBits) == 64)
|
||||
val storegen = new StoreGen(io.typ, io.addr, io.rhs)
|
||||
val rhs = storegen.wordData
|
||||
|
||||
@ -639,27 +614,27 @@ class AMOALU(implicit conf: DCacheConfig) extends Module {
|
||||
io.out := wmask & out | ~wmask & io.lhs
|
||||
}
|
||||
|
||||
class HellaCacheReq(implicit val conf: DCacheConfig) extends BundleWithConf {
|
||||
class HellaCacheReq extends Bundle {
|
||||
val kill = Bool()
|
||||
val typ = Bits(width = MT_SZ)
|
||||
val phys = Bool()
|
||||
val addr = UInt(width = conf.maxaddrbits)
|
||||
val data = Bits(width = conf.databits)
|
||||
val tag = Bits(width = conf.reqtagbits)
|
||||
val addr = UInt(width = params(MaxAddrBits))
|
||||
val data = Bits(width = params(CoreDataBits))
|
||||
val tag = Bits(width = params(CoreReqTagBits))
|
||||
val cmd = Bits(width = M_SZ)
|
||||
}
|
||||
|
||||
class HellaCacheResp(implicit val conf: DCacheConfig) extends BundleWithConf {
|
||||
class HellaCacheResp extends Bundle {
|
||||
val nack = Bool() // comes 2 cycles after req.fire
|
||||
val replay = Bool()
|
||||
val typ = Bits(width = 3)
|
||||
val has_data = Bool()
|
||||
val data = Bits(width = conf.databits)
|
||||
val data_subword = Bits(width = conf.databits)
|
||||
val tag = Bits(width = conf.reqtagbits)
|
||||
val data = Bits(width = params(CoreDataBits))
|
||||
val data_subword = Bits(width = params(CoreDataBits))
|
||||
val tag = Bits(width = params(CoreReqTagBits))
|
||||
val cmd = Bits(width = 4)
|
||||
val addr = UInt(width = conf.maxaddrbits)
|
||||
val store_data = Bits(width = conf.databits)
|
||||
val addr = UInt(width = params(MaxAddrBits))
|
||||
val store_data = Bits(width = params(CoreDataBits))
|
||||
}
|
||||
|
||||
class AlignmentExceptions extends Bundle {
|
||||
@ -673,26 +648,33 @@ class HellaCacheExceptions extends Bundle {
|
||||
}
|
||||
|
||||
// interface between D$ and processor/DTLB
|
||||
class HellaCacheIO(implicit conf: DCacheConfig) extends Bundle {
|
||||
class HellaCacheIO extends Bundle {
|
||||
val req = Decoupled(new HellaCacheReq)
|
||||
val resp = Valid(new HellaCacheResp).flip
|
||||
val replay_next = Valid(Bits(width = conf.reqtagbits)).flip
|
||||
val replay_next = Valid(Bits(width = params(CoreReqTagBits))).flip
|
||||
val xcpt = (new HellaCacheExceptions).asInput
|
||||
val ptw = new TLBPTWIO()(conf.as).flip
|
||||
val ptw = new TLBPTWIO().flip
|
||||
val ordered = Bool(INPUT)
|
||||
}
|
||||
|
||||
class HellaCache(implicit conf: DCacheConfig) extends Module {
|
||||
implicit val (tl, ln) = (conf.tl, conf.tl.ln)
|
||||
class HellaCache extends Module {
|
||||
val co = params(TLCoherence)
|
||||
val io = new Bundle {
|
||||
val cpu = (new HellaCacheIO).flip
|
||||
val mem = new TileLinkIO
|
||||
}
|
||||
|
||||
val indexmsb = conf.untagbits-1
|
||||
val indexlsb = conf.offbits
|
||||
require(params(LRSCCycles) >= 32) // ISA requires 16-insn LRSC sequences to succeed
|
||||
require(isPow2(params(NSets)))
|
||||
require(isPow2(params(NWays))) // TODO: relax this
|
||||
require(params(RowBits) <= params(TLDataBits))
|
||||
require(params(PAddrBits)-params(OffBits) == params(TLAddrBits) )
|
||||
require(params(UntagBits) <= params(PgIdxBits))
|
||||
|
||||
val indexmsb = params(UntagBits)-1
|
||||
val indexlsb = params(OffBits)
|
||||
val offsetmsb = indexlsb-1
|
||||
val offsetlsb = log2Up(conf.databytes)
|
||||
val offsetlsb = params(WordOffBits)
|
||||
|
||||
val wb = Module(new WritebackUnit)
|
||||
val prober = Module(new ProbeUnit)
|
||||
@ -721,12 +703,12 @@ class HellaCache(implicit conf: DCacheConfig) extends Module {
|
||||
val s1_sc = s1_req.cmd === M_XSC
|
||||
val s1_readwrite = s1_read || s1_write || isPrefetch(s1_req.cmd)
|
||||
|
||||
val dtlb = Module(new TLB(conf.ntlb)(conf.as))
|
||||
val dtlb = Module(new TLB(params(NTLBEntries)))
|
||||
dtlb.io.ptw <> io.cpu.ptw
|
||||
dtlb.io.req.valid := s1_valid_masked && s1_readwrite && !s1_req.phys
|
||||
dtlb.io.req.bits.passthrough := s1_req.phys
|
||||
dtlb.io.req.bits.asid := UInt(0)
|
||||
dtlb.io.req.bits.vpn := s1_req.addr >> conf.pgidxbits
|
||||
dtlb.io.req.bits.vpn := s1_req.addr >> params(PgIdxBits)
|
||||
dtlb.io.req.bits.instruction := Bool(false)
|
||||
when (!dtlb.io.req.ready && !io.cpu.req.bits.phys) { io.cpu.req.ready := Bool(false) }
|
||||
|
||||
@ -734,11 +716,11 @@ class HellaCache(implicit conf: DCacheConfig) extends Module {
|
||||
s1_req := io.cpu.req.bits
|
||||
}
|
||||
when (wb.io.meta_read.valid) {
|
||||
s1_req.addr := Cat(wb.io.meta_read.bits.tag, wb.io.meta_read.bits.idx) << conf.offbits
|
||||
s1_req.addr := Cat(wb.io.meta_read.bits.tag, wb.io.meta_read.bits.idx) << params(OffBits)
|
||||
s1_req.phys := Bool(true)
|
||||
}
|
||||
when (prober.io.meta_read.valid) {
|
||||
s1_req.addr := Cat(prober.io.meta_read.bits.tag, prober.io.meta_read.bits.idx) << conf.offbits
|
||||
s1_req.addr := Cat(prober.io.meta_read.bits.tag, prober.io.meta_read.bits.idx) << params(OffBits)
|
||||
s1_req.phys := Bool(true)
|
||||
}
|
||||
when (mshrs.io.replay.valid) {
|
||||
@ -747,7 +729,7 @@ class HellaCache(implicit conf: DCacheConfig) extends Module {
|
||||
when (s2_recycle) {
|
||||
s1_req := s2_req
|
||||
}
|
||||
val s1_addr = Cat(dtlb.io.resp.ppn, s1_req.addr(conf.pgidxbits-1,0))
|
||||
val s1_addr = Cat(dtlb.io.resp.ppn, s1_req.addr(params(PgIdxBits)-1,0))
|
||||
|
||||
when (s1_clk_en) {
|
||||
s2_req.kill := s1_req.kill
|
||||
@ -773,7 +755,7 @@ class HellaCache(implicit conf: DCacheConfig) extends Module {
|
||||
io.cpu.xcpt.pf.st := s1_write && dtlb.io.resp.xcpt_st
|
||||
|
||||
// tags
|
||||
def onReset = L1Metadata(UInt(0), ClientMetadata(UInt(0))(tl.co))
|
||||
def onReset = L1Metadata(UInt(0), ClientMetadata(UInt(0))(co))
|
||||
val meta = Module(new MetadataArray(onReset _))
|
||||
val metaReadArb = Module(new Arbiter(new MetaReadReq, 5))
|
||||
val metaWriteArb = Module(new Arbiter(new L1MetaWriteReq, 2))
|
||||
@ -787,12 +769,12 @@ class HellaCache(implicit conf: DCacheConfig) extends Module {
|
||||
data.io.write.valid := writeArb.io.out.valid
|
||||
writeArb.io.out.ready := data.io.write.ready
|
||||
data.io.write.bits := writeArb.io.out.bits
|
||||
val wdata_encoded = (0 until conf.rowwords).map(i => conf.code.encode(writeArb.io.out.bits.data(conf.databits*(i+1)-1,conf.databits*i)))
|
||||
val wdata_encoded = (0 until params(RowWords)).map(i => params(ECCCode).encode(writeArb.io.out.bits.data(params(CoreDataBits)*(i+1)-1,params(CoreDataBits)*i)))
|
||||
data.io.write.bits.data := Vec(wdata_encoded).toBits
|
||||
|
||||
// tag read for new requests
|
||||
metaReadArb.io.in(4).valid := io.cpu.req.valid
|
||||
metaReadArb.io.in(4).bits.idx := io.cpu.req.bits.addr >> conf.offbits
|
||||
metaReadArb.io.in(4).bits.idx := io.cpu.req.bits.addr >> params(OffBits)
|
||||
when (!metaReadArb.io.in(4).ready) { io.cpu.req.ready := Bool(false) }
|
||||
|
||||
// data read for new requests
|
||||
@ -803,34 +785,34 @@ class HellaCache(implicit conf: DCacheConfig) extends Module {
|
||||
|
||||
// recycled requests
|
||||
metaReadArb.io.in(0).valid := s2_recycle
|
||||
metaReadArb.io.in(0).bits.idx := s2_req.addr >> conf.offbits
|
||||
metaReadArb.io.in(0).bits.idx := s2_req.addr >> params(OffBits)
|
||||
readArb.io.in(0).valid := s2_recycle
|
||||
readArb.io.in(0).bits.addr := s2_req.addr
|
||||
readArb.io.in(0).bits.way_en := SInt(-1)
|
||||
|
||||
// tag check and way muxing
|
||||
def wayMap[T <: Data](f: Int => T) = Vec((0 until conf.ways).map(f))
|
||||
val s1_tag_eq_way = wayMap((w: Int) => meta.io.resp(w).tag === (s1_addr >> conf.untagbits)).toBits
|
||||
val s1_tag_match_way = wayMap((w: Int) => s1_tag_eq_way(w) && tl.co.isValid(meta.io.resp(w).coh)).toBits
|
||||
def wayMap[T <: Data](f: Int => T) = Vec((0 until params(NWays)).map(f))
|
||||
val s1_tag_eq_way = wayMap((w: Int) => meta.io.resp(w).tag === (s1_addr >> params(UntagBits))).toBits
|
||||
val s1_tag_match_way = wayMap((w: Int) => s1_tag_eq_way(w) && co.isValid(meta.io.resp(w).coh)).toBits
|
||||
s1_clk_en := metaReadArb.io.out.valid //TODO: should be metaReadArb.io.out.fire(), but triggers Verilog backend bug
|
||||
val s1_writeback = s1_clk_en && !s1_valid && !s1_replay
|
||||
val s2_tag_match_way = RegEnable(s1_tag_match_way, s1_clk_en)
|
||||
val s2_tag_match = s2_tag_match_way.orR
|
||||
val s2_hit_state = Mux1H(s2_tag_match_way, wayMap((w: Int) => RegEnable(meta.io.resp(w).coh, s1_clk_en)))
|
||||
val s2_hit = s2_tag_match && tl.co.isHit(s2_req.cmd, s2_hit_state) && s2_hit_state === tl.co.clientMetadataOnHit(s2_req.cmd, s2_hit_state)
|
||||
val s2_hit = s2_tag_match && co.isHit(s2_req.cmd, s2_hit_state) && s2_hit_state === co.clientMetadataOnHit(s2_req.cmd, s2_hit_state)
|
||||
|
||||
// load-reserved/store-conditional
|
||||
val lrsc_count = Reg(init=UInt(0))
|
||||
val lrsc_valid = lrsc_count.orR
|
||||
val lrsc_addr = Reg(UInt())
|
||||
val (s2_lr, s2_sc) = (s2_req.cmd === M_XLR, s2_req.cmd === M_XSC)
|
||||
val s2_lrsc_addr_match = lrsc_valid && lrsc_addr === (s2_req.addr >> conf.offbits)
|
||||
val s2_lrsc_addr_match = lrsc_valid && lrsc_addr === (s2_req.addr >> params(OffBits))
|
||||
val s2_sc_fail = s2_sc && !s2_lrsc_addr_match
|
||||
when (lrsc_valid) { lrsc_count := lrsc_count - 1 }
|
||||
when (s2_valid_masked && s2_hit || s2_replay) {
|
||||
when (s2_lr) {
|
||||
when (!lrsc_valid) { lrsc_count := conf.lrsc_cycles-1 }
|
||||
lrsc_addr := s2_req.addr >> conf.offbits
|
||||
when (!lrsc_valid) { lrsc_count := params(LRSCCycles)-1 }
|
||||
lrsc_addr := s2_req.addr >> params(OffBits)
|
||||
}
|
||||
when (s2_sc) {
|
||||
lrsc_count := 0
|
||||
@ -838,21 +820,21 @@ class HellaCache(implicit conf: DCacheConfig) extends Module {
|
||||
}
|
||||
when (io.cpu.ptw.sret) { lrsc_count := 0 }
|
||||
|
||||
val s2_data = Vec.fill(conf.ways){Bits(width = conf.encrowbits)}
|
||||
for (w <- 0 until conf.ways) {
|
||||
val regs = Vec.fill(conf.rowwords){Reg(Bits(width = conf.encdatabits))}
|
||||
val s2_data = Vec.fill(params(NWays)){Bits(width = params(EncRowBits))}
|
||||
for (w <- 0 until params(NWays)) {
|
||||
val regs = Vec.fill(params(RowWords)){Reg(Bits(width = params(EncDataBits)))}
|
||||
val en1 = s1_clk_en && s1_tag_eq_way(w)
|
||||
for (i <- 0 until regs.size) {
|
||||
val en = en1 && (Bool(i == 0 || !conf.isNarrowRead) || s1_writeback)
|
||||
when (en) { regs(i) := data.io.resp(w) >> conf.encdatabits*i }
|
||||
val en = en1 && ((Bool(i == 0) || !params(DoNarrowRead)) || s1_writeback)
|
||||
when (en) { regs(i) := data.io.resp(w) >> params(EncDataBits)*i }
|
||||
}
|
||||
s2_data(w) := regs.toBits
|
||||
}
|
||||
val s2_data_muxed = Mux1H(s2_tag_match_way, s2_data)
|
||||
val s2_data_decoded = (0 until conf.rowwords).map(i => conf.code.decode(s2_data_muxed(conf.encdatabits*(i+1)-1,conf.encdatabits*i)))
|
||||
val s2_data_decoded = (0 until params(RowWords)).map(i => params(ECCCode).decode(s2_data_muxed(params(EncDataBits)*(i+1)-1,params(EncDataBits)*i)))
|
||||
val s2_data_corrected = Vec(s2_data_decoded.map(_.corrected)).toBits
|
||||
val s2_data_uncorrected = Vec(s2_data_decoded.map(_.uncorrected)).toBits
|
||||
val s2_word_idx = if (conf.isNarrowRead) UInt(0) else s2_req.addr(log2Up(conf.rowwords*conf.databytes)-1,3)
|
||||
val s2_word_idx = if (params(DoNarrowRead)) UInt(0) else s2_req.addr(log2Up(params(RowWords)*params(CoreDataBytes))-1,3)
|
||||
val s2_data_correctable = Vec(s2_data_decoded.map(_.correctable)).toBits()(s2_word_idx)
|
||||
|
||||
// store/amo hits
|
||||
@ -865,15 +847,15 @@ class HellaCache(implicit conf: DCacheConfig) extends Module {
|
||||
}
|
||||
|
||||
writeArb.io.in(0).bits.addr := s3_req.addr
|
||||
writeArb.io.in(0).bits.wmask := UInt(1) << (if(conf.rowoffbits > offsetlsb)
|
||||
s3_req.addr(conf.rowoffbits-1,offsetlsb).toUInt
|
||||
writeArb.io.in(0).bits.wmask := UInt(1) << (if(params(RowOffBits) > offsetlsb)
|
||||
s3_req.addr(params(RowOffBits)-1,offsetlsb).toUInt
|
||||
else UInt(0))
|
||||
writeArb.io.in(0).bits.data := Fill(conf.rowwords, s3_req.data)
|
||||
writeArb.io.in(0).bits.data := Fill(params(RowWords), s3_req.data)
|
||||
writeArb.io.in(0).valid := s3_valid
|
||||
writeArb.io.in(0).bits.way_en := s3_way
|
||||
|
||||
// replacement policy
|
||||
val replacer = new RandomReplacement
|
||||
val replacer = params(Replacer)()
|
||||
val s1_replaced_way_en = UIntToOH(replacer.way)
|
||||
val s2_replaced_way_en = UIntToOH(RegEnable(replacer.way, s1_clk_en))
|
||||
val s2_repl_meta = Mux1H(s2_replaced_way_en, wayMap((w: Int) => RegEnable(meta.io.resp(w), s1_clk_en && s1_replaced_way_en(w))).toSeq)
|
||||
@ -914,9 +896,9 @@ class HellaCache(implicit conf: DCacheConfig) extends Module {
|
||||
prober.io.mshr_rdy := mshrs.io.probe_rdy
|
||||
|
||||
// refills
|
||||
def doRefill(g: Grant): Bool = tl.co.messageUpdatesDataArray(g)
|
||||
val refill = if(conf.refillcycles > 1) {
|
||||
val ser = Module(new FlowThroughSerializer(io.mem.grant.bits, conf.refillcycles, doRefill))
|
||||
def doRefill(g: Grant): Bool = co.messageUpdatesDataArray(g)
|
||||
val refill = if(params(RefillCycles) > 1) {
|
||||
val ser = Module(new FlowThroughSerializer(io.mem.grant.bits, params(RefillCycles), doRefill))
|
||||
ser.io.in <> io.mem.grant
|
||||
ser.io.out
|
||||
} else io.mem.grant
|
||||
@ -926,7 +908,7 @@ class HellaCache(implicit conf: DCacheConfig) extends Module {
|
||||
writeArb.io.in(1).valid := refill.valid && doRefill(refill.bits.payload)
|
||||
writeArb.io.in(1).bits := mshrs.io.mem_resp
|
||||
writeArb.io.in(1).bits.wmask := SInt(-1)
|
||||
writeArb.io.in(1).bits.data := refill.bits.payload.data(conf.encrowbits-1,0)
|
||||
writeArb.io.in(1).bits.data := refill.bits.payload.data(params(EncRowBits)-1,0)
|
||||
readArb.io.out.ready := !refill.valid || refill.ready // insert bubble if refill gets blocked
|
||||
readArb.io.out <> data.io.read
|
||||
|
||||
@ -947,8 +929,8 @@ class HellaCache(implicit conf: DCacheConfig) extends Module {
|
||||
((s2_valid_masked || s2_replay) && !s2_sc_fail, s2_req, amoalu.io.out),
|
||||
(s3_valid, s3_req, s3_req.data),
|
||||
(s4_valid, s4_req, s4_req.data)
|
||||
).map(r => (r._1 && (s1_addr >> conf.wordoffbits === r._2.addr >> conf.wordoffbits) && isWrite(r._2.cmd), r._3))
|
||||
val s2_store_bypass_data = Reg(Bits(width = conf.databits))
|
||||
).map(r => (r._1 && (s1_addr >> params(WordOffBits) === r._2.addr >> params(WordOffBits)) && isWrite(r._2.cmd), r._3))
|
||||
val s2_store_bypass_data = Reg(Bits(width = params(CoreDataBits)))
|
||||
val s2_store_bypass = Reg(Bool())
|
||||
when (s1_clk_en) {
|
||||
s2_store_bypass := false
|
||||
@ -959,7 +941,7 @@ class HellaCache(implicit conf: DCacheConfig) extends Module {
|
||||
}
|
||||
|
||||
// load data subword mux/sign extension
|
||||
val s2_data_word_prebypass = s2_data_uncorrected >> Cat(s2_word_idx, Bits(0,log2Up(conf.databits)))
|
||||
val s2_data_word_prebypass = s2_data_uncorrected >> Cat(s2_word_idx, Bits(0,log2Up(params(CoreDataBits))))
|
||||
val s2_data_word = Mux(s2_store_bypass, s2_store_bypass_data, s2_data_word_prebypass)
|
||||
val loadgen = new LoadGen(s2_req.typ, s2_req.addr, s2_data_word, s2_sc)
|
||||
|
||||
@ -1006,7 +988,7 @@ class HellaCache(implicit conf: DCacheConfig) extends Module {
|
||||
}
|
||||
|
||||
// exposes a sane decoupled request interface
|
||||
class SimpleHellaCacheIF(implicit conf: DCacheConfig) extends Module
|
||||
class SimpleHellaCacheIF extends Module
|
||||
{
|
||||
val io = new Bundle {
|
||||
val requestor = new HellaCacheIO().flip
|
||||
|
||||
Reference in New Issue
Block a user