riscv/rocket-chip
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Full conversion to params. Compiles but does not elaborate.

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This commit is contained in:
Henry Cook
2014-08-08 12:23:02 -07:00
parent 4e6d69892d
commit 0dac9a7467
15 changed files with 500 additions and 560 deletions
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160
rocket/src/main/scala/icache.scala
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@ -4,62 +4,39 @@ import Chisel._
import uncore._
import Util._
case class ICacheConfig(sets: Int, assoc: Int,
ibytes: Int = 4, rowbytes: Int = 16,
ntlb: Int = 8,
tl: TileLinkConfiguration,
as: AddressSpaceConfiguration,
btb: BTBConfig,
code: Code = new IdentityCode)
{
val w = 1
case object InstBytes extends Field[Int]
case object CoreBTBParams extends Field[PF]
val dm = assoc == 1
val lines = sets * assoc
val idxbits = log2Up(sets)
val offbits = log2Up(tl.dataBits/8)
val rowbits = rowbytes*8
val rowoffbits = log2Up(rowbytes)
val untagbits = idxbits + offbits
val tagbits = as.paddrBits - untagbits
val refillcycles = tl.dataBits/rowbits
require(isPow2(sets) && isPow2(assoc))
require(isPow2(w) && isPow2(ibytes))
require(as.pgIdxBits >= untagbits)
class FrontendReq extends Bundle {
val pc = UInt(width = params(VAddrBits)+1)
}
class FrontendReq()(implicit val conf: ICacheConfig) extends BundleWithConf {
val pc = UInt(width = conf.as.vaddrBits+1)
}
class FrontendResp(implicit val conf: ICacheConfig) extends BundleWithConf {
val pc = UInt(width = conf.as.vaddrBits+1) // ID stage PC
val data = Bits(width = conf.ibytes*8)
class FrontendResp extends Bundle {
val pc = UInt(width = params(VAddrBits)+1) // ID stage PC
val data = Bits(width = params(InstBytes)*8)
val xcpt_ma = Bool()
val xcpt_if = Bool()
}
class CPUFrontendIO(implicit conf: ICacheConfig) extends Bundle {
class CPUFrontendIO extends Bundle {
val req = Valid(new FrontendReq)
val resp = Decoupled(new FrontendResp).flip
val btb_resp = Valid(new BTBResp()(conf.btb)).flip
val btb_update = Valid(new BTBUpdate()(conf.btb))
val ptw = new TLBPTWIO()(conf.as).flip
val btb_resp = Valid(new BTBResp).flip
val btb_update = Valid(new BTBUpdate)
val ptw = new TLBPTWIO().flip
val invalidate = Bool(OUTPUT)
}
class Frontend(implicit c: ICacheConfig) extends Module
class Frontend extends Module
{
implicit val (tl, as) = (c.tl, c.as)
val io = new Bundle {
val cpu = new CPUFrontendIO()(c).flip
val cpu = new CPUFrontendIO().flip
val mem = new UncachedTileLinkIO
}
val btb = Module(new BTB()(c.btb))
val btb = Module(new BTB, params(CoreBTBParams))
val icache = Module(new ICache)
val tlb = Module(new TLB(c.ntlb))
val tlb = Module(new TLB(params(NTLBEntries)))
val s1_pc_ = Reg(UInt())
val s1_pc = s1_pc_ & SInt(-2) // discard LSB of PC (throughout the pipeline)
@ -70,14 +47,14 @@ class Frontend(implicit c: ICacheConfig) extends Module
val s2_btb_resp_bits = Reg(btb.io.resp.bits.clone)
val s2_xcpt_if = Reg(init=Bool(false))
val msb = c.as.vaddrBits-1
val msb = params(VAddrBits)-1
val btbTarget = Cat(btb.io.resp.bits.target(msb), btb.io.resp.bits.target)
val pcp4_0 = s1_pc + UInt(c.ibytes)
val pcp4_0 = s1_pc + UInt(params(InstBytes))
val pcp4 = Cat(s1_pc(msb) & pcp4_0(msb), pcp4_0(msb,0))
val icmiss = s2_valid && !icache.io.resp.valid
val predicted_npc = Mux(btb.io.resp.bits.taken, btbTarget, pcp4)
val npc = Mux(icmiss, s2_pc, predicted_npc).toUInt
val s0_same_block = !icmiss && !io.cpu.req.valid && !btb.io.resp.bits.taken && ((pcp4 & c.rowbytes) === (s1_pc & c.rowbytes))
val s0_same_block = !icmiss && !io.cpu.req.valid && !btb.io.resp.bits.taken && ((pcp4 & params(RowBytes)) === (s1_pc & params(RowBytes)))
val stall = io.cpu.resp.valid && !io.cpu.resp.ready
when (!stall) {
@ -97,13 +74,13 @@ class Frontend(implicit c: ICacheConfig) extends Module
s2_valid := Bool(false)
}
btb.io.req := s1_pc & SInt(-c.ibytes)
btb.io.req := s1_pc & SInt(-params(InstBytes))
btb.io.update := io.cpu.btb_update
btb.io.invalidate := io.cpu.invalidate || io.cpu.ptw.invalidate
tlb.io.ptw <> io.cpu.ptw
tlb.io.req.valid := !stall && !icmiss
tlb.io.req.bits.vpn := s1_pc >> UInt(c.as.pgIdxBits)
tlb.io.req.bits.vpn := s1_pc >> UInt(params(PgIdxBits))
tlb.io.req.bits.asid := UInt(0)
tlb.io.req.bits.passthrough := Bool(false)
tlb.io.req.bits.instruction := Bool(true)
@ -117,35 +94,38 @@ class Frontend(implicit c: ICacheConfig) extends Module
icache.io.resp.ready := !stall && !s1_same_block
io.cpu.resp.valid := s2_valid && (s2_xcpt_if || icache.io.resp.valid)
io.cpu.resp.bits.pc := s2_pc & SInt(-c.ibytes) // discard PC LSBs
io.cpu.resp.bits.data := icache.io.resp.bits.datablock >> (s2_pc(log2Up(c.rowbytes)-1,log2Up(c.ibytes)) << log2Up(c.ibytes*8))
io.cpu.resp.bits.xcpt_ma := s2_pc(log2Up(c.ibytes)-1,0) != UInt(0)
io.cpu.resp.bits.pc := s2_pc & SInt(-params(InstBytes)) // discard PC LSBs
io.cpu.resp.bits.data := icache.io.resp.bits.datablock >> (s2_pc(log2Up(params(RowBytes))-1,log2Up(params(InstBytes))) << log2Up(params(InstBytes)*8))
io.cpu.resp.bits.xcpt_ma := s2_pc(log2Up(params(InstBytes))-1,0) != UInt(0)
io.cpu.resp.bits.xcpt_if := s2_xcpt_if
io.cpu.btb_resp.valid := s2_btb_resp_valid
io.cpu.btb_resp.bits := s2_btb_resp_bits
}
class ICacheReq(implicit val conf: ICacheConfig) extends BundleWithConf {
val idx = UInt(width = conf.as.pgIdxBits)
val ppn = UInt(width = conf.as.ppnBits) // delayed one cycle
class ICacheReq extends Bundle {
val idx = UInt(width = params(PgIdxBits))
val ppn = UInt(width = params(PPNBits)) // delayed one cycle
val kill = Bool() // delayed one cycle
}
class ICacheResp(implicit val conf: ICacheConfig) extends BundleWithConf {
val data = Bits(width = conf.ibytes*8)
val datablock = Bits(width = conf.rowbits)
class ICacheResp extends Bundle {
val data = Bits(width = params(InstBytes)*8)
val datablock = Bits(width = params(RowBits))
}
class ICache(implicit c: ICacheConfig) extends Module
class ICache extends Module
{
implicit val (tl, ln) = (c.tl, c.tl.ln)
val (nSets, nWays, co, ecc) = (params(NSets), params(NWays), params(TLCoherence), params(ECCCode))
val io = new Bundle {
val req = Valid(new ICacheReq).flip
val resp = Decoupled(new ICacheResp)
val invalidate = Bool(INPUT)
val mem = new UncachedTileLinkIO
}
require(isPow2(nSets) && isPow2(nWays))
require(isPow2(params(InstBytes)))
require(params(PgIdxBits) >= params(UntagBits))
val s_ready :: s_request :: s_refill_wait :: s_refill :: Nil = Enum(UInt(), 4)
val state = Reg(init=s_ready)
@ -154,13 +134,13 @@ class ICache(implicit c: ICacheConfig) extends Module
val rdy = Bool()
val s2_valid = Reg(init=Bool(false))
val s2_addr = Reg(UInt(width = c.as.paddrBits))
val s2_addr = Reg(UInt(width = params(PAddrBits)))
val s2_any_tag_hit = Bool()
val s1_valid = Reg(init=Bool(false))
val s1_pgoff = Reg(UInt(width = c.as.pgIdxBits))
val s1_pgoff = Reg(UInt(width = params(PgIdxBits)))
val s1_addr = Cat(io.req.bits.ppn, s1_pgoff).toUInt
val s1_tag = s1_addr(c.tagbits+c.untagbits-1,c.untagbits)
val s1_tag = s1_addr(params(TagBits)+params(UntagBits)-1,params(UntagBits))
val s0_valid = io.req.valid || s1_valid && stall
val s0_pgoff = Mux(s1_valid && stall, s1_pgoff, io.req.bits.idx)
@ -175,9 +155,9 @@ class ICache(implicit c: ICacheConfig) extends Module
s2_addr := s1_addr
}
val s2_tag = s2_addr(c.tagbits+c.untagbits-1,c.untagbits)
val s2_idx = s2_addr(c.untagbits-1,c.offbits)
val s2_offset = s2_addr(c.offbits-1,0)
val s2_tag = s2_addr(params(TagBits)+params(UntagBits)-1,params(UntagBits))
val s2_idx = s2_addr(params(UntagBits)-1,params(OffBits))
val s2_offset = s2_addr(params(OffBits)-1,0)
val s2_hit = s2_valid && s2_any_tag_hit
val s2_miss = s2_valid && !s2_any_tag_hit
rdy := state === s_ready && !s2_miss
@ -187,8 +167,8 @@ class ICache(implicit c: ICacheConfig) extends Module
var refill_valid = io.mem.grant.valid
var refill_bits = io.mem.grant.bits
def doRefill(g: Grant): Bool = Bool(true)
if(c.refillcycles > 1) {
val ser = Module(new FlowThroughSerializer(io.mem.grant.bits, c.refillcycles, doRefill))
if(params(RefillCycles) > 1) {
val ser = Module(new FlowThroughSerializer(io.mem.grant.bits, params(RefillCycles), doRefill))
ser.io.in <> io.mem.grant
refill_cnt = ser.io.cnt
refill_done = ser.io.done
@ -200,21 +180,21 @@ class ICache(implicit c: ICacheConfig) extends Module
}
//assert(!c.tlco.isVoluntary(refill_bits.payload) || !refill_valid, "UncachedRequestors shouldn't get voluntary grants.")
val repl_way = if (c.dm) UInt(0) else LFSR16(s2_miss)(log2Up(c.assoc)-1,0)
val enc_tagbits = c.code.width(c.tagbits)
val tag_array = Mem(Bits(width = enc_tagbits*c.assoc), c.sets, seqRead = true)
val repl_way = if (params(IsDM)) UInt(0) else LFSR16(s2_miss)(log2Up(nWays)-1,0)
val entagbits = ecc.width(params(TagBits))
val tag_array = Mem(Bits(width = entagbits*nWays), nSets, seqRead = true)
val tag_raddr = Reg(UInt())
when (refill_done) {
val wmask = FillInterleaved(enc_tagbits, if (c.dm) Bits(1) else UIntToOH(repl_way))
val tag = c.code.encode(s2_tag).toUInt
tag_array.write(s2_idx, Fill(c.assoc, tag), wmask)
val wmask = FillInterleaved(entagbits, if (params(IsDM)) Bits(1) else UIntToOH(repl_way))
val tag = ecc.encode(s2_tag).toUInt
tag_array.write(s2_idx, Fill(nWays, tag), wmask)
}
// /*.else*/when (s0_valid) { // uncomment ".else" to infer 6T SRAM
.elsewhen (s0_valid) {
tag_raddr := s0_pgoff(c.untagbits-1,c.offbits)
tag_raddr := s0_pgoff(params(UntagBits)-1,params(OffBits))
}
val vb_array = Reg(init=Bits(0, c.lines))
val vb_array = Reg(init=Bits(0, nSets*nWays))
when (refill_done && !invalidated) {
vb_array := vb_array.bitSet(Cat(repl_way, s2_idx), Bool(true))
}
@ -222,59 +202,59 @@ class ICache(implicit c: ICacheConfig) extends Module
vb_array := Bits(0)
invalidated := Bool(true)
}
val s2_disparity = Vec.fill(c.assoc){Bool()}
for (i <- 0 until c.assoc)
val s2_disparity = Vec.fill(nWays){Bool()}
for (i <- 0 until nWays)
when (s2_valid && s2_disparity(i)) { vb_array := vb_array.bitSet(Cat(UInt(i), s2_idx), Bool(false)) }
val s1_tag_match = Vec.fill(c.assoc){Bool()}
val s2_tag_hit = Vec.fill(c.assoc){Bool()}
val s2_dout = Vec.fill(c.assoc){Reg(Bits())}
val s1_tag_match = Vec.fill(nWays){Bool()}
val s2_tag_hit = Vec.fill(nWays){Bool()}
val s2_dout = Vec.fill(nWays){Reg(Bits())}
for (i <- 0 until c.assoc) {
val s1_vb = vb_array(Cat(UInt(i), s1_pgoff(c.untagbits-1,c.offbits))).toBool
for (i <- 0 until nWays) {
val s1_vb = vb_array(Cat(UInt(i), s1_pgoff(params(UntagBits)-1,params(OffBits)))).toBool
val s2_vb = Reg(Bool())
val s2_tag_disparity = Reg(Bool())
val s2_tag_match = Reg(Bool())
val tag_out = tag_array(tag_raddr)(enc_tagbits*(i+1)-1, enc_tagbits*i)
val tag_out = tag_array(tag_raddr)(entagbits*(i+1)-1, entagbits*i)
when (s1_valid && rdy && !stall) {
s2_vb := s1_vb
s2_tag_disparity := c.code.decode(tag_out).error
s2_tag_disparity := ecc.decode(tag_out).error
s2_tag_match := s1_tag_match(i)
}
s1_tag_match(i) := tag_out(c.tagbits-1,0) === s1_tag
s1_tag_match(i) := tag_out(params(TagBits)-1,0) === s1_tag
s2_tag_hit(i) := s2_vb && s2_tag_match
s2_disparity(i) := s2_vb && (s2_tag_disparity || c.code.decode(s2_dout(i)).error)
s2_disparity(i) := s2_vb && (s2_tag_disparity || ecc.decode(s2_dout(i)).error)
}
s2_any_tag_hit := s2_tag_hit.reduceLeft(_||_) && !s2_disparity.reduceLeft(_||_)
for (i <- 0 until c.assoc) {
val data_array = Mem(Bits(width = c.code.width(c.rowbits)), c.sets*c.refillcycles, seqRead = true)
for (i <- 0 until nWays) {
val data_array = Mem(Bits(width = ecc.width(params(RowBits))), nSets*params(RefillCycles), seqRead = true)
val s1_raddr = Reg(UInt())
when (refill_valid && repl_way === UInt(i)) {
val e_d = c.code.encode(refill_bits.payload.data)
if(c.refillcycles > 1) data_array(Cat(s2_idx,refill_cnt)) := e_d
val e_d = ecc.encode(refill_bits.payload.data)
if(params(RefillCycles) > 1) data_array(Cat(s2_idx,refill_cnt)) := e_d
else data_array(s2_idx) := e_d
}
// /*.else*/when (s0_valid) { // uncomment ".else" to infer 6T SRAM
.elsewhen (s0_valid) {
s1_raddr := s0_pgoff(c.untagbits-1,c.offbits-(if(c.refillcycles > 1) refill_cnt.getWidth else 0))
s1_raddr := s0_pgoff(params(UntagBits)-1,params(OffBits)-(if(params(RefillCycles) > 1) refill_cnt.getWidth else 0))
}
// if s1_tag_match is critical, replace with partial tag check
when (s1_valid && rdy && !stall && (Bool(c.dm) || s1_tag_match(i))) { s2_dout(i) := data_array(s1_raddr) }
when (s1_valid && rdy && !stall && (Bool(params(IsDM)) || s1_tag_match(i))) { s2_dout(i) := data_array(s1_raddr) }
}
val s2_dout_word = s2_dout.map(x => (x >> (s2_offset(log2Up(c.rowbytes)-1,log2Up(c.ibytes)) << log2Up(c.ibytes*8)))(c.ibytes*8-1,0))
val s2_dout_word = s2_dout.map(x => (x >> (s2_offset(log2Up(params(RowBytes))-1,log2Up(params(InstBytes))) << log2Up(params(InstBytes)*8)))(params(InstBytes)*8-1,0))
io.resp.bits.data := Mux1H(s2_tag_hit, s2_dout_word)
io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout)
val ack_q = Module(new Queue(new LogicalNetworkIO(new Finish), 1))
ack_q.io.enq.valid := refill_done && tl.co.requiresAckForGrant(refill_bits.payload.g_type)
ack_q.io.enq.valid := refill_done && co.requiresAckForGrant(refill_bits.payload.g_type)
ack_q.io.enq.bits.payload.master_xact_id := refill_bits.payload.master_xact_id
ack_q.io.enq.bits.header.dst := refill_bits.header.src
// output signals
io.resp.valid := s2_hit
io.mem.acquire.valid := (state === s_request) && ack_q.io.enq.ready
io.mem.acquire.bits.payload := Acquire(tl.co.getUncachedReadAcquireType, s2_addr >> UInt(c.offbits), UInt(0))
io.mem.acquire.bits.payload := Acquire(co.getUncachedReadAcquireType, s2_addr >> UInt(params(OffBits)), UInt(0))
io.mem.finish <> ack_q.io.deq
// control state machine