riscv/rocket-chip
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Full conversion to params. Compiles but does not elaborate.

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This commit is contained in:
Henry Cook
2014-08-08 12:23:02 -07:00
parent 4e6d69892d
commit 0dac9a7467
15 changed files with 500 additions and 560 deletions
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112
rocket/src/main/scala/btb.scala
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@ -3,61 +3,63 @@ package rocket
import Chisel._
import Util._
import Node._
import uncore._
case class BTBConfig(as: uncore.AddressSpaceConfiguration, entries: Int, nras: Int = 0) {
val matchBits = as.pgIdxBits
val pages0 = 1 max log2Up(entries) // is this sensible?
val pages = (pages0+1)/2*2 // control logic assumes 2 divides pages
val opaqueBits = log2Up(entries)
val nbht = 1 << log2Up(entries * 2)
}
case object Entries extends Field[Int]
case object NRAS extends Field[Int]
case object MatchBits extends Field[Int]
case object Pages0 extends Field[Int]
case object Pages extends Field[Int]
case object OpaqueBits extends Field[Int]
case object NBHT extends Field[Int]
class RAS(implicit conf: BTBConfig) {
class RAS(nras: Int) {
def push(addr: UInt): Unit = {
when (count < conf.nras) { count := count + 1 }
val nextPos = Mux(Bool(isPow2(conf.nras)) || pos > 0, pos+1, UInt(0))
when (count < nras) { count := count + 1 }
val nextPos = Mux(Bool(isPow2(nras)) || pos > 0, pos+1, UInt(0))
stack(nextPos) := addr
pos := nextPos
}
def peek: UInt = stack(pos)
def pop: Unit = when (!isEmpty) {
count := count - 1
pos := Mux(Bool(isPow2(conf.nras)) || pos > 0, pos-1, UInt(conf.nras-1))
pos := Mux(Bool(isPow2(nras)) || pos > 0, pos-1, UInt(nras-1))
}
def clear: Unit = count := UInt(0)
def isEmpty: Bool = count === UInt(0)
private val count = Reg(init=UInt(0,log2Up(conf.nras+1)))
private val pos = Reg(init=UInt(0,log2Up(conf.nras)))
private val stack = Vec.fill(conf.nras){Reg(UInt())}
private val count = Reg(init=UInt(0,log2Up(nras+1)))
private val pos = Reg(init=UInt(0,log2Up(nras)))
private val stack = Vec.fill(nras){Reg(UInt())}
}
class BHTResp(implicit conf: BTBConfig) extends Bundle {
val index = UInt(width = log2Up(conf.nbht).max(1))
class BHTResp extends Bundle {
val index = UInt(width = log2Up(params(NBHT)).max(1))
val value = UInt(width = 2)
}
class BHT(implicit conf: BTBConfig) {
class BHT(nbht: Int) {
val nbhtbits = log2Up(nbht)
def get(addr: UInt): BHTResp = {
val res = new BHTResp
res.index := addr(log2Up(conf.nbht)+1,2) ^ history
res.index := addr(nbhtbits+1,2) ^ history
res.value := table(res.index)
res
}
def update(d: BHTResp, taken: Bool): Unit = {
table(d.index) := Cat(taken, (d.value(1) & d.value(0)) | ((d.value(1) | d.value(0)) & taken))
history := Cat(taken, history(log2Up(conf.nbht)-1,1))
history := Cat(taken, history(nbhtbits-1,1))
}
private val table = Mem(UInt(width = 2), conf.nbht)
val history = Reg(UInt(width = log2Up(conf.nbht)))
private val table = Mem(UInt(width = 2), nbht)
val history = Reg(UInt(width = nbhtbits))
}
class BTBUpdate(implicit val conf: BTBConfig) extends BundleWithConf {
class BTBUpdate extends Bundle {
val prediction = Valid(new BTBResp)
val pc = UInt(width = conf.as.vaddrBits)
val target = UInt(width = conf.as.vaddrBits)
val returnAddr = UInt(width = conf.as.vaddrBits)
val pc = UInt(width = params(VAddrBits))
val target = UInt(width = params(VAddrBits))
val returnAddr = UInt(width = params(VAddrBits))
val taken = Bool()
val isJump = Bool()
val isCall = Bool()
@ -65,42 +67,42 @@ class BTBUpdate(implicit val conf: BTBConfig) extends BundleWithConf {
val incorrectTarget = Bool()
}
class BTBResp(implicit val conf: BTBConfig) extends BundleWithConf {
class BTBResp extends Bundle {
val taken = Bool()
val target = UInt(width = conf.as.vaddrBits)
val entry = UInt(width = conf.opaqueBits)
val target = UInt(width = params(VAddrBits))
val entry = UInt(width = params(OpaqueBits))
val bht = new BHTResp
}
// fully-associative branch target buffer
class BTB(implicit conf: BTBConfig) extends Module {
class BTB extends Module {
val io = new Bundle {
val req = UInt(INPUT, conf.as.vaddrBits)
val req = UInt(INPUT, params(VAddrBits))
val resp = Valid(new BTBResp)
val update = Valid(new BTBUpdate).flip
val invalidate = Bool(INPUT)
}
val idxValid = Reg(init=UInt(0, conf.entries))
val idxs = Mem(UInt(width=conf.matchBits), conf.entries)
val idxPages = Mem(UInt(width=log2Up(conf.pages)), conf.entries)
val tgts = Mem(UInt(width=conf.matchBits), conf.entries)
val tgtPages = Mem(UInt(width=log2Up(conf.pages)), conf.entries)
val pages = Mem(UInt(width=conf.as.vaddrBits-conf.matchBits), conf.pages)
val pageValid = Reg(init=UInt(0, conf.pages))
val idxPagesOH = idxPages.map(UIntToOH(_)(conf.pages-1,0))
val tgtPagesOH = tgtPages.map(UIntToOH(_)(conf.pages-1,0))
val idxValid = Reg(init=UInt(0, params(Entries)))
val idxs = Mem(UInt(width=params(MatchBits)), params(Entries))
val idxPages = Mem(UInt(width=log2Up(params(Pages))), params(Entries))
val tgts = Mem(UInt(width=params(MatchBits)), params(Entries))
val tgtPages = Mem(UInt(width=log2Up(params(Pages))), params(Entries))
val pages = Mem(UInt(width=params(VAddrBits)-params(MatchBits)), params(Pages))
val pageValid = Reg(init=UInt(0, params(Pages)))
val idxPagesOH = idxPages.map(UIntToOH(_)(params(Pages)-1,0))
val tgtPagesOH = tgtPages.map(UIntToOH(_)(params(Pages)-1,0))
val useRAS = Reg(UInt(width = conf.entries))
val isJump = Reg(UInt(width = conf.entries))
val useRAS = Reg(UInt(width = params(Entries)))
val isJump = Reg(UInt(width = params(Entries)))
private def page(addr: UInt) = addr >> conf.matchBits
private def page(addr: UInt) = addr >> params(MatchBits)
private def pageMatch(addr: UInt) = {
val p = page(addr)
Vec(pages.map(_ === p)).toBits & pageValid
}
private def tagMatch(addr: UInt, pgMatch: UInt): UInt = {
val idx = addr(conf.matchBits-1,0)
val idx = addr(params(MatchBits)-1,0)
val idxMatch = idxs.map(_ === idx).toBits
val idxPageMatch = idxPagesOH.map(_ & pgMatch).map(_.orR).toBits
idxValid & idxMatch & idxPageMatch
@ -121,7 +123,7 @@ class BTB(implicit conf: BTBConfig) extends Module {
}
val updateHit = update.bits.prediction.valid
val updateValid = update.bits.incorrectTarget || updateHit && Bool(conf.nbht > 0)
val updateValid = update.bits.incorrectTarget || updateHit && Bool(params(NBHT) > 0)
val updateTarget = updateValid && update.bits.incorrectTarget
val useUpdatePageHit = updatePageHit.orR
@ -134,20 +136,20 @@ class BTB(implicit conf: BTBConfig) extends Module {
val samePage = page(update.bits.pc) === page(update_target)
val usePageHit = (pageHit & ~idxPageReplEn).orR
val doTgtPageRepl = updateTarget && !samePage && !usePageHit
val tgtPageRepl = Mux(samePage, idxPageUpdateOH, idxPageUpdateOH(conf.pages-2,0) << 1 | idxPageUpdateOH(conf.pages-1))
val tgtPageRepl = Mux(samePage, idxPageUpdateOH, idxPageUpdateOH(params(Pages)-2,0) << 1 | idxPageUpdateOH(params(Pages)-1))
val tgtPageUpdate = OHToUInt(Mux(usePageHit, pageHit, tgtPageRepl))
val tgtPageReplEn = Mux(doTgtPageRepl, tgtPageRepl, UInt(0))
val doPageRepl = doIdxPageRepl || doTgtPageRepl
val pageReplEn = idxPageReplEn | tgtPageReplEn
idxPageRepl := UIntToOH(Counter(update.valid && doPageRepl, conf.pages)._1)
idxPageRepl := UIntToOH(Counter(update.valid && doPageRepl, params(Pages))._1)
when (update.valid && !(updateValid && !updateTarget)) {
val nextRepl = Counter(!updateHit && updateValid, conf.entries)._1
val nextRepl = Counter(!updateHit && updateValid, params(Entries))._1
val waddr = Mux(updateHit, update.bits.prediction.bits.entry, nextRepl)
// invalidate entries if we stomp on pages they depend upon
idxValid := idxValid & ~Vec.tabulate(conf.entries)(i => (pageReplEn & (idxPagesOH(i) | tgtPagesOH(i))).orR).toBits
idxValid := idxValid & ~Vec.tabulate(params(Entries))(i => (pageReplEn & (idxPagesOH(i) | tgtPagesOH(i))).orR).toBits
idxValid(waddr) := updateValid
when (updateTarget) {
@ -160,11 +162,11 @@ class BTB(implicit conf: BTBConfig) extends Module {
isJump(waddr) := update.bits.isJump
}
require(conf.pages % 2 == 0)
val idxWritesEven = (idxPageUpdateOH & Fill(conf.pages/2, UInt(1,2))).orR
require(params(Pages) % 2 == 0)
val idxWritesEven = (idxPageUpdateOH & Fill(params(Pages)/2, UInt(1,2))).orR
def writeBank(i: Int, mod: Int, en: Bool, data: UInt) =
for (i <- i until conf.pages by mod)
for (i <- i until params(Pages) by mod)
when (en && pageReplEn(i)) { pages(i) := data }
writeBank(0, 2, Mux(idxWritesEven, doIdxPageRepl, doTgtPageRepl),
@ -185,16 +187,16 @@ class BTB(implicit conf: BTBConfig) extends Module {
io.resp.bits.target := Cat(Mux1H(Mux1H(hits, tgtPagesOH), pages), Mux1H(hits, tgts))
io.resp.bits.entry := OHToUInt(hits)
if (conf.nbht > 0) {
val bht = new BHT
if (params(NBHT) > 0) {
val bht = new BHT(params(NBHT))
val res = bht.get(io.req)
when (update.valid && updateHit && !update.bits.isJump) { bht.update(update.bits.prediction.bits.bht, update.bits.taken) }
when (!res.value(0) && !Mux1H(hits, isJump)) { io.resp.bits.taken := false }
io.resp.bits.bht := res
}
if (conf.nras > 0) {
val ras = new RAS
if (params(NRAS) > 0) {
val ras = new RAS(params(NRAS))
val doPeek = Mux1H(hits, useRAS)
when (!ras.isEmpty && doPeek) {
io.resp.bits.target := ras.peek