riscv/rocket-chip
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fixed init pin generation

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This commit is contained in:
Huy Vo 2013-04-20 00:38:01 -07:00
parent a01cdf95fd
commit 0d87e3bacc
1 changed files with 4 additions and 3 deletions
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7
src/main/scala/RocketChip.scala
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@ -276,16 +276,16 @@ class ReferenceChipBackend extends VerilogBackend
def addMemPin(c: Component) = { def addMemPin(c: Component) = {
for (node <- Component.nodes) { for (node <- Component.nodes) {
if (node.isInstanceOf[Mem[ _ ]] && node.component != null && node.asInstanceOf[Mem[_]].seqRead) { if (node.isInstanceOf[Mem[ _ ]] && node.component != null && node.asInstanceOf[Mem[_]].seqRead) {
val init = Bool(INPUT) val init = Bool()
init.setName("init") init.setName("init_node")
node.inputs += init node.inputs += init
init.component = node.component
connectMemPin(c, node.component, init) connectMemPin(c, node.component, init)
} }
} }
} }
def connectMemPin(topC: Component, c: Component, p: Bool): Unit = { def connectMemPin(topC: Component, c: Component, p: Bool): Unit = {
p.component = c
var isNewPin = false var isNewPin = false
val compInitPin = val compInitPin =
if (initMap.contains(c)) { if (initMap.contains(c)) {
@ -300,6 +300,7 @@ class ReferenceChipBackend extends VerilogBackend
if (isNewPin) { if (isNewPin) {
compInitPin.setName("init") compInitPin.setName("init")
c.io.asInstanceOf[Bundle] += compInitPin c.io.asInstanceOf[Bundle] += compInitPin
compInitPin.component = c
initMap += (c -> compInitPin) initMap += (c -> compInitPin)
connectMemPin(topC, c.parent, compInitPin) connectMemPin(topC, c.parent, compInitPin)
} }