riscv/rocket-chip
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make sure conf address map scales with number of cores

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This commit is contained in:
Howard Mao
2015-09-25 09:41:19 -07:00
parent 5e3f9115d3
commit 0d763524ef
1 changed files with 12 additions and 3 deletions
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15
src/main/scala/Configs.scala
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@@ -15,6 +15,16 @@ class DefaultConfig extends ChiselConfig (
topDefinitions = { (pname,site,here) =>
type PF = PartialFunction[Any,Any]
def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
def genCsrAddrMap() = {
val xLen = site(XLen)
val nSCR = site(HTIFNSCR)
val csrSize = (1 << 12) * (xLen / 8)
val nTiles = site(NTiles)
(0 until nTiles)
.map(i => (s"csr$i", None, MemSize(csrSize, AddrMap.RW))) :+
("scr", None, MemSize(nSCR * xLen / 8, AddrMap.RW))
}
pname match {
//
case UseZscale => false
@@ -159,9 +169,8 @@ class DefaultConfig extends ChiselConfig (
case ExternalIOStart => 2 * site(MMIOBase)
case NASTIAddrMap => Seq(
("mem", None, MemSize(site(MMIOBase), AddrMap.RWX)),
("conf", None, Submap(site(ExternalIOStart) - site(MMIOBase),
("csr0", None, MemSize(1 << 15, AddrMap.RW)),
("scr", None, MemSize(site(HTIFNSCR) * 8, AddrMap.RW)))),
("conf", None, MemSubmap(site(ExternalIOStart) - site(MMIOBase),
genCsrAddrMap())),
("io", Some(site(ExternalIOStart)),
MemSize(2 * site(MMIOBase), AddrMap.RW)))
case NASTIAddrHashMap => new AddrHashMap(site(NASTIAddrMap))