riscv/rocket-chip
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rocket icache: tie off b ready

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Wesley W. Terpstra 2017-03-19 17:18:50 -07:00
parent c9459fe4eb
commit 0c92283a61
1 changed files with 1 additions and 0 deletions
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src/main/scala/rocket/ICache.scala
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@ -156,6 +156,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
fromSource = UInt(0), fromSource = UInt(0),
toAddress = (refill_addr >> blockOffBits) << blockOffBits, toAddress = (refill_addr >> blockOffBits) << blockOffBits,
lgSize = lgCacheBlockBytes)._2 lgSize = lgCacheBlockBytes)._2
tl_out.b.ready := Bool(true)
tl_out.c.valid := Bool(false) tl_out.c.valid := Bool(false)
tl_out.e.valid := Bool(false) tl_out.e.valid := Bool(false)