ahb: implement a ToTL bridge
This commit is contained in:
Wesley W. Terpstra
parent
7f71df0925
commit
0c5fd76089
@ -43,10 +43,6 @@ case class AHBSlavePortParameters(
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// Check that the link can be implemented in AHB
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require (maxTransfer <= beatBytes * AHBParameters.maxTransfer)
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lazy val routingMask = AddressDecoder(slaves.map(_.address))
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def findSafe(address: UInt) = Vec(slaves.map(_.address.map(_.contains(address)).reduce(_ || _)))
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def findFast(address: UInt) = Vec(slaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))
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// Require disjoint ranges for addresses
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slaves.combinations(2).foreach { case Seq(x,y) =>
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x.address.foreach { a => y.address.foreach { b =>
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139
src/main/scala/uncore/ahb/ToTL.scala
Normal file
139
src/main/scala/uncore/ahb/ToTL.scala
Normal file
@ -0,0 +1,139 @@
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// See LICENSE.SiFive for license details.
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package uncore.ahb
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import config._
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import diplomacy._
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import uncore.tilelink2._
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case class AHBToTLNode() extends MixedAdapterNode(AHBImp, TLImp)(
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dFn = { case AHBMasterPortParameters(masters) =>
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TLClientPortParameters(clients = masters.map { m =>
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TLClientParameters(nodePath = m.nodePath)
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})
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},
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uFn = { mp => AHBSlavePortParameters(
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slaves = mp.managers.map { m =>
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def adjust(x: TransferSizes) = {
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if (x.contains(mp.beatBytes)) {
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TransferSizes(x.min, m.minAlignment.min(mp.beatBytes * AHBParameters.maxTransfer).toInt)
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} else { // larger than beatBytes requires beatBytes if misaligned
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x.intersect(TransferSizes(1, mp.beatBytes))
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}
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}
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AHBSlaveParameters(
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address = m.address,
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resources = m.resources,
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regionType = m.regionType,
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executable = m.executable,
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nodePath = m.nodePath,
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supportsWrite = adjust(m.supportsPutFull),
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supportsRead = adjust(m.supportsGet))},
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beatBytes = mp.beatBytes)
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})
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class AHBToTL()(implicit p: Parameters) extends LazyModule
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{
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val node = AHBToTLNode()
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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val out = node.bundleOut
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}
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((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
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val beatBytes = edgeOut.manager.beatBytes
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val d_send = RegInit(Bool(false))
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val d_recv = RegInit(Bool(false))
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val d_error = RegInit(Bool(false))
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val d_pause = RegInit(Bool(false))
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val d_write = RegInit(Bool(false))
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val d_addr = Reg(in.haddr)
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val d_size = Reg(in.hsize)
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when (out.d.valid) { d_recv := Bool(false); d_error := d_error || out.d.bits.error }
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when (out.a.ready) { d_send := Bool(false) }
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val a_count = RegInit(UInt(0, width = 4))
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val a_first = a_count === UInt(0)
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val d_last = a_first
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val burst_sizes = Seq(1, 1, 4, 4, 8, 8, 16, 16)
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val a_burst_size = Vec(burst_sizes.map(beats => UInt(log2Ceil(beats * beatBytes))))(in.hburst)
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val a_burst_mask = Vec(burst_sizes.map(beats => UInt(beats * beatBytes - 1)))(in.hburst)
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val a_burst_ok =
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in.htrans === AHBParameters.TRANS_NONSEQ && // only start burst on first AHB beat
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in.hsize === UInt(log2Ceil(beatBytes)) && // not a narrow burst
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(in.haddr & a_burst_mask) === UInt(0) && // address aligned to burst size
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in.hburst =/= AHBParameters.BURST_INCR && // we know the burst length a priori
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Mux(in.hwrite, // target device supports the burst
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edgeOut.manager.supportsPutFullSafe(in.haddr, a_burst_size),
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edgeOut.manager.supportsGetSafe (in.haddr, a_burst_size))
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val beat = TransferSizes(1, beatBytes)
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val a_legal = // Is the single-beat access allowed?
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Mux(in.hwrite,
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edgeOut.manager.supportsPutFullSafe(in.haddr, in.hsize, Some(beat)),
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edgeOut.manager.supportsGetSafe (in.haddr, in.hsize, Some(beat)))
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val a_access = in.htrans === AHBParameters.TRANS_NONSEQ || in.htrans === AHBParameters.TRANS_SEQ
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val a_accept = in.hready && in.hsel && a_access
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when (a_accept) {
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a_count := a_count - UInt(1)
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d_error := d_error || !a_legal
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when ( in.hwrite) { d_send := Bool(true) }
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when (!in.hwrite) { d_recv := Bool(true) }
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when (a_first) {
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a_count := Mux(a_burst_ok, a_burst_mask >> log2Ceil(beatBytes), UInt(0))
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d_send := a_legal
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d_recv := a_legal
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d_error := !a_legal
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d_pause := Bool(false)
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d_write := in.hwrite
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d_addr := in.haddr
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d_size := Mux(a_burst_ok, a_burst_size, in.hsize)
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}
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}
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out.a.valid := d_send
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out.a.bits.opcode := Mux(d_write, TLMessages.PutFullData, TLMessages.Get)
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out.a.bits.param := UInt(0)
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out.a.bits.size := d_size
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out.a.bits.source := UInt(0)
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out.a.bits.address := d_addr
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out.a.bits.data := in.hwdata
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out.a.bits.mask := maskGen(d_addr, d_size, beatBytes)
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// Save the error for the last beat (so the master can't cancel the burst)
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// When we report an error, we need to be hreadyout LOW for one cycle
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val inject_error = d_last && (d_error || (out.d.valid && out.d.bits.error))
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when (inject_error) { d_pause := Bool(true) }
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out.d.ready := d_recv // backpressure AccessAckData arriving faster than AHB beats
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in.hrdata := out.d.bits.data
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in.hresp := inject_error
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in.hreadyout := (!inject_error || d_pause) && Mux(d_write, (!d_send || out.a.ready) && (!d_last || !d_recv || out.d.valid), out.d.valid || !d_recv)
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// Unused channels
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out.b.ready := Bool(true)
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out.c.valid := Bool(false)
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out.e.valid := Bool(false)
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}
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}
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}
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object AHBToTL
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{
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def apply()(x: AHBOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
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val tl = LazyModule(new AHBToTL)
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tl.node := x
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tl.node
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}
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}
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