Assertion for back-to-back uncached and cached ops (#631)
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		@@ -180,6 +180,12 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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  io.cpu.s2_nack := s2_valid && !s2_valid_hit && !(s2_valid_uncached && tl_out.a.ready && !uncachedInFlight.asUInt.andR)
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					  io.cpu.s2_nack := s2_valid && !s2_valid_hit && !(s2_valid_uncached && tl_out.a.ready && !uncachedInFlight.asUInt.andR)
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  when (io.cpu.s2_nack || (s2_valid_hit && s2_update_meta)) { s1_nack := true }
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					  when (io.cpu.s2_nack || (s2_valid_hit && s2_update_meta)) { s1_nack := true }
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					  val s3_valid = Reg(next = s2_valid, init=Bool(false))
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					  val s3_uncached = Reg(next = s2_uncached, init=Bool(false))
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					  when (s2_valid_cached_miss) {
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					    assert( !(s3_valid && s3_uncached) )
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					  }
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  // exceptions
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					  // exceptions
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  val s1_storegen = new StoreGen(s1_req.typ, s1_req.addr, UInt(0), wordBytes)
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					  val s1_storegen = new StoreGen(s1_req.typ, s1_req.addr, UInt(0), wordBytes)
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  val no_xcpt = Bool(usingDataScratchpad) && s1_req.phys /* slave port */ && s1_hit_state.isValid()
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					  val no_xcpt = Bool(usingDataScratchpad) && s1_req.phys /* slave port */ && s1_hit_state.isValid()
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