riscv/rocket-chip
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Avoid zero-width wire case :-/

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This commit is contained in:
Andrew Waterman 2016-01-12 15:32:29 -08:00
parent a953ff384a
commit 0b90b8fe5f
1 changed files with 4 additions and 1 deletions
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5
uncore/src/main/scala/tilelink.scala
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@ -169,8 +169,11 @@ trait HasAcquireUnion extends HasTileLinkParameters {
def amo_shift_bytes(dummy: Int = 0) = UInt(amoAluOperandBytes)*amo_offset() def amo_shift_bytes(dummy: Int = 0) = UInt(amoAluOperandBytes)*amo_offset()
/** Write mask for [[uncore.Put]], [[uncore.PutBlock]], [[uncore.PutAtomic]] */ /** Write mask for [[uncore.Put]], [[uncore.PutBlock]], [[uncore.PutAtomic]] */
def wmask(dummy: Int = 0): UInt = { def wmask(dummy: Int = 0): UInt = {
val amo_word_mask =
if (amoAluOperandBytes == tlWriteMaskBits) UInt(1)
else UIntToOH(amo_offset())
Mux(isBuiltInType(Acquire.putAtomicType), Mux(isBuiltInType(Acquire.putAtomicType),
FillInterleaved(amoAluOperandBits/8, UIntToOH(amo_offset())), FillInterleaved(amoAluOperandBytes, amo_word_mask),
Mux(isBuiltInType(Acquire.putBlockType) || isBuiltInType(Acquire.putType), Mux(isBuiltInType(Acquire.putBlockType) || isBuiltInType(Acquire.putType),
union(tlWriteMaskBits, 1), union(tlWriteMaskBits, 1),
UInt(0, width = tlWriteMaskBits))) UInt(0, width = tlWriteMaskBits)))